Travelled to:1 × France
5 × USA
Collaborated with:S.Kang R.Panda D.Blaauw T.Edwards S.Pullela G.Vija J.Norton Y.Cheng C.Teng E.Rosenbaum R.Vaidyanathan B.Tutuianu D.Bearden S.Sirichotiyakul C.Oh J.Zuo
Talks about:circuit (4) design (3) power (3) worst (2) minim (2) vlsi (2) size (2) cmos (2) chip (2) case (2)
Person: Abhijit Dharchoudhury
DBLP: Dharchoudhury:Abhijit
Contributed to:
19991998
1998199619931992Wrote 7 papers:
- DAC-1999-SirichotiyakulEOZDPB #power management
- Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing (SS, TE, CO, JZ, AD, RP, DB), pp. 436–441.
- DAC-1998-DharchoudhuryPBVTB #analysis #design #network
- Design and Analysis of Power Distribution Networks in PowerPC Microprocessors (AD, RP, DB, RV, BT, DB), pp. 738–743.
- DAC-1998-PandaDENB #design #incremental #migration #named
- Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization (RP, AD, TE, JN, DB), pp. 388–391.
- DATE-1998-PullelaPDV
- CMOS Combinational Circuit Sizing by Stage-wise Tapering (SP, RP, AD, GV), pp. 985–986.
- DAC-1996-ChengTDRK #named #reliability
- iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips (YKC, CCT, AD, ER, SMK), pp. 548–551.
- DAC-1993-DharchoudhuryK #variability #worst-case
- Performance-Constrained Worst-Case Variability Minimization of VLSI Circuits (AD, SMK), pp. 154–158.
- DAC-1992-DharchoudhuryK #approach #design #optimisation #worst-case
- An Integrated Approach to Realistic Worst-Case Design Optimization of MOS Analog Circuits (AD, SMK), pp. 704–709.