BibSLEIGH — Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics

Peter Feldmann, Sharad Kapur, David E. Long
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
DATE, 1999.

DATE 1999

@inproceedings{DATE-1999-FeldmanKL,
	author        = "Peter Feldmann and Sharad Kapur and David E. Long",
	booktitle     = "{Proceedings of the Fourth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1109/DATE.1999.761158",
	isbn          = "0-7695-0078-1",
	pages         = "418--417",
	publisher     = "{IEEE Computer Society}",
	title         = "{Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics}",
	year          = 1999,
}

Peter Feldmann, Sharad Kapur, David E. LongEfficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package ParasiticsDATE, 1999.

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Peter Feldmann, Sharad Kapur, David E. Long
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics
DATE, 1999.