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Travelled to:
1 × Germany
5 × France
6 × USA
Collaborated with:
S.Abbaspour R.W.Freund A.Demir V.Zolotov F.Liu S.Kapur D.E.Long R.C.Melville D.D.Ling C.Visweswariah S.Hatami M.Pedram H.G.Brachtendorf S.Lampe R.Laur D.Sinha G.Schaeffer R.Banerji H.Gupta L.Ye F.Chang R.Chadha N.Ns F.Cano A.Dunlop J.S.Roychowdhury
Talks about:
model (8) linear (4) time (4) waveform (3) order (3) larg (3) techniqu (2) parasit (2) circuit (2) analysi (2)

Person: Peter Feldmann

DBLP DBLP: Feldmann:Peter

Contributed to:

DAC 20152015
DAC 20142014
DAC 20092009
DATE 20092009
DAC 20082008
DATE v2 20042004
DATE 20022002
DATE 20002000
DATE 19991999
DAC 19981998
DATE 19981998
DAC 19951995

Wrote 14 papers:

DAC-2015-ZolotovF #integer #linear #programming
Variation aware cross-talk aggressor alignment by mixed integer linear programming (VZ, PF), p. 6.
A Time-Unrolling Method to Compute Sensitivity of Dynamic Systems (FL, PF), p. 6.
DAC-2009-LingVFA #analysis #effectiveness
A moment-based effective characterization waveform for static timing analysis (DDL, CV, PF, SA), pp. 19–24.
DATE-2009-HatamiFAP #library #performance
Efficient compression and handling of current source model library waveforms (SH, PF, SA, MP), pp. 1178–1183.
DAC-2008-FeldmannA #approach #modelling #physics #towards
Towards a more physical approach to gate modeling for timing, noise, and power (PF, SA), pp. 453–455.
DAC-2008-FeldmannASSBG #analysis #modelling #multi
Driver waveform computation for timing analysis with multiple voltage threshold driver models (PF, SA, DS, GS, RB, HG), pp. 425–428.
DATE-v2-2004-Feldmann #linear #order #reduction #scalability
Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals (PF), pp. 944–947.
DATE-2002-BrachtendorfLLMF #continuation #using
Steady State Calculation of Oscillators Using Continuation Methods (HGB, SL, RL, RCM, PF), p. 1139.
DATE-2000-DemirF #evaluation #modelling #performance #probability
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits (AD, PF), pp. 340–344.
DATE-1999-FeldmanKL #modelling #performance
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics (PF, SK, DEL), pp. 418–417.
DATE-1999-YeCFCNC #design #verification
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs (LY, FCC, PF, RC, NN, FC), pp. 658–663.
DAC-1998-DunlopDFKLMR #design #tool support
Tools and Methodology for RF IC Design (AD, AD, PF, SK, DEL, RCM, JSR), pp. 414–420.
DATE-1998-FreundF #approximate #linear #modelling #multi #scalability #using
Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Pade Approximation (RWF, PF), pp. 530–537.
DAC-1995-FeldmannF #algorithm #linear #modelling #scalability
Reduced-Order Modeling of Large Linear Subcircuits via a Block Lanczos Algorithm (PF, RWF), pp. 474–479.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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