Proceedings of the Fourth Conference on Design, Automation and Test in Europe
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Proceedings of the Fourth Conference on Design, Automation and Test in Europe
DATE, 1999.

SYS
DBLP
Scholar
Full names Links ISxN
@proceedings{DATE-1999,
	address       = "Munich, Germany",
	isbn          = "0-7695-0078-1",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Fourth Conference on Design, Automation and Test in Europe}",
	year          = 1999,
}

Contents (144 items)

DATE-1999-Seepold #component #reuse #using
Reuse of IP and virtual components (RS).
DATE-1999-Junkkari #challenge #complexity #design #development #testing
Higher Product Complexity and Shorter Development Time — Continuous Challenge to Design and Test Environment (JJ), pp. 2–3.
DATE-1999-Thoma #challenge
Automotive Electronics — A Challenge For Systems Engineering (PT), p. 4.
DATE-1999-Williams #testing
Testing in Nanometer Technologies (TWW), p. 5–?.
DATE-1999-CabodiCPQ #simulation
Computing Timed Transition Relations for Sequential Cycle-Based Simulation (GC, PC, CP, SQ), pp. 8–12.
DATE-1999-HongB #analysis #finite #reachability #scalability #state machine #using
Symbolic Reachability Analysis of Large Finite State Machines Using Don’t Cares (YH, PAB), p. 13–?.
DATE-1999-HwangVH #clustering #functional #power management
FSMD Functional Partitioning for Low Power (EH, FV, YCH), pp. 22–27.
DATE-1999-JochensKSN #component #megamodelling
A New Parameterizable Power Macro-Model for Datapath Components (GJ, LK, ES, WN), p. 29–?.
DATE-1999-ReutterR #design #performance #reuse
An Efficient Reuse System for Digital Circuit Design (AR, WR), pp. 38–43.
DATE-1999-IkedaKNSYMNO #architecture #scalability #video
An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative Architecture (MI, TK, KN, KS, TY, TM, JN, TO), p. 44–?.
DATE-1999-HorethD #specification #verification
Formal Verification of Word-Level Specifications (SH, RD), pp. 52–57.
DATE-1999-EvekingHR #automation #scheduling #synthesis #verification
Automatic Verification of Scheduling Results in High-Level Synthesis (HE, HH, GR), pp. 59–64.
DATE-1999-HuhnSKL #verification
Verifying Imprecisely Working Arithmetic Circuits (MH, KS, TK, GL), p. 65–?.
DATE-1999-PedramW #design
Battery-Powered Digital CMOS Design (MP, QW), pp. 72–76.
DATE-1999-ChungBBM #power management
Dynamic Power Management for non-stationary service requests (EYC, LB, AB, GDM), pp. 77–81.
DATE-1999-MurgaiF #on the
On Reducing Transitions Through Data Modifications (RM, MF), p. 82–?.
DATE-1999-MaestreKBSHF #configuration management #kernel #scheduling
Kernel Scheduling in Reconfigurable Computing (RM, FJK, NB, HS, RH, MF), pp. 90–96.
DATE-1999-Dav #configuration management #distributed #embedded #hardware #named #realtime
CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems (BPD), pp. 97–104.
DATE-1999-Leupers #code generation #embedded
Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors (RL), p. 105–?.
DATE-1999-NikolosVHT #embedded #fault #testing
Path Delay Fault Testing of ICs with Embedded Intellectual Property Blocks (DN, HTV, TH, YT), pp. 112–116.
DATE-1999-PaschalisKPGZ #architecture #effectiveness #multi #performance
An Effective BIST Architecture for Fast Multiplier Cores (AMP, NK, MP, DG, YZ), pp. 117–121.
DATE-1999-NoufalN #framework #generative #multi #self
A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes (IAN, MN), p. 122–?.
DATE-1999-MukherjeeJTFAF #approach #performance #verification
An Efficient Filter-Based Approach for Combinational Verification (RM, JJ, KT, MF, JAA, DSF), pp. 132–137.
DATE-1999-RanjanSSB #using #verification
Using Combinational Verification for Sequential Circuits (RKR, VS, FS, RKB), pp. 138–144.
DATE-1999-Marques-SilvaG #equivalence #learning #recursion #satisfiability #using
Combinational Equivalence Checking Using Satisfiability and Recursive Learning (JPMS, TG), pp. 145–149.
DATE-1999-HendricxC
Formally Verified Redundancy Removal (SH, LJMC), p. 150–?.
DATE-1999-KimKHL #logic #power management #synthesis
Logic Transformation for Low Power Synthesis (KWK, SMK, TH, CLL), pp. 158–162.
DATE-1999-BeniniMMMPS #power management
Glitch Power Minimization by Gate Freezing (LB, GDM, AM, EM, MP, RS), pp. 163–167.
DATE-1999-NoethK #encoding #power management
Spanning Tree-based State Encoding for Low Power Dissipation (WN, RK), pp. 168–174.
DATE-1999-Hsiao #estimation #optimisation #scalability #search-based #using
Peak Power Estimation Using Genetic Spot Optimization for Large VLSI Circuits (MSH), p. 175–?.
DATE-1999-CotaCL #adaptation #fault #linear #using
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester (ÉFC, LC, ML), pp. 184–188.
DATE-1999-GomesC #testing #using
Minimal Length Diagnostic Tests for Analog Circuits using Test History (AVG, AC), pp. 189–194.
DATE-1999-CherubalC #fault #functional #parametricity #using
Parametric Fault Diagnosis for Analog Systems Using Functional Mapping (SC, AC), p. 195–?.
DATE-1999-KaulV #clustering #design #latency #runtime
Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs (MK, RV), pp. 202–209.
DATE-1999-JaschkeLB #resource management #scheduling
Time Constrained Modulo Scheduling with Global Resource Sharing (CJ, RL, FB), pp. 210–216.
DATE-1999-SmithM #component #polynomial
Polynomial Methods for Allocating Complex Components (JS, GDM), pp. 217–222.
DATE-1999-MansouriV #design #verification
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs (NM, RV), p. 223–?.
DATE-1999-LechnerFRH #automation #performance #self
A Digital Partial Built-In Self-Test for a High Performance Automatic Gain Control Circuit (AL, JF, AR, BH), pp. 232–238.
DATE-1999-LatorreBHPN #design #modelling
Design, Characterization & Modelling of a CMOS Magnetic Field Sensor (LL, YB, PH, FP, PN), pp. 239–243.
DATE-1999-YangZ #fault #performance #robust #simulation
Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog Circuits (ZRY, MZ), pp. 244–248.
DATE-1999-NovakHK #analysis #on the
On Analog Signature Analysis (FN, BH, SK), p. 249–?.
DATE-1999-JantschKH #analysis #case study #concept #modelling #synthesis
The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems (AJ, SK, AH), pp. 256–262.
DATE-1999-DickJ #multi #named #synthesis
MOCSYN: Multiobjective Core-Based Single-Chip System Synthesis (RPD, NKJ), pp. 263–270.
DATE-1999-CmarRSVB #design #fixpoint #refinement
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement (RC, LR, PS, SV, IB), p. 271–?.
DATE-1999-CarlettaNP #synthesis #testing
Synthesis of Controllers for Full Testability of Integrated Datapath-Controller Pairs (JC, MN, CAP), pp. 278–282.
DATE-1999-MakrisO #behaviour #reachability #synthesis
Channel-Based Behavioral Test Synthesis for Improved Module Reachability (YM, AO), pp. 283–288.
DATE-1999-NicoliciA #hardware #performance
Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data Paths (NN, BMAH), p. 289–?.
DATE-1999-OchiaiINEO #embedded #framework #performance #platform #video
High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV Scalabilit (KO, HI, JN, ME, TO), pp. 303–308.
DATE-1999-TabbaraSSFL #modelling #performance #using
Fast Hardware-Software Co-simulation Using VHDL Models (BT, MS, ALSV, EF, LL), p. 309–?.
DATE-1999-VerhoevenS #feedback
Systematic Biasing of Negative Feedback Amplifiers (CJMV, AvS), pp. 318–322.
DATE-1999-SchwenckerEGA #automation #constraints
Automating the Sizing of Analog CMOS Circuits by Consideration of Structural Constraints (RS, JE, HEG, KA), pp. 323–327.
DATE-1999-DhanwadaNV #constraints #synthesis #using
Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis (NRD, ANA, RV), p. 328–?.
DATE-1999-DoboliV #architecture #behaviour #compilation #generative #synthesis
A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems (AD, RV), pp. 338–345.
DATE-1999-BreuerMBFLK #reasoning #semantics #using
Reasoning about VHDL and VHDL-AMS using Denotational Semantics (PTB, NMM, JPB, RBF, MMLP, CDK), pp. 346–352.
DATE-1999-Sasaki #semantics #simulation #state machine
A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine (HS), p. 353–?.
DATE-1999-AntakiSXA #design #testing
Design For Testability Method for CML Digital Circuits (BA, YS, NX, SA), pp. 360–367.
DATE-1999-FavalliM #design #functional #on the #self
On the Design of Self-Checking Functional Units Based on Shannon Circuits (MF, CM), pp. 368–375.
DATE-1999-NiggemeyerR #parametricity #self
Parametric Built-In Self-Test of VLSI Systems (DN, MR), p. 376–?.
DATE-1999-Micheli #c #c++ #hardware #modelling #synthesis
Hardware Synthesis from C/C++ Models (GDM), pp. 382–383.
DATE-1999-Arnout #c #design
C for System Level Design (GA), pp. 384–386.
DATE-1999-GhoshKL #c #c++ #hardware #synthesis
Hardware Synthesis from C/C++ (AG, JK, SYL), pp. 387–389.
DATE-1999-Wakabayashi #behaviour #case study #experience #synthesis
C-based Synthesis Experiences with a Behavior Synthesizer, “Cyber” (KW), p. 390–?.
DATE-1999-CostaSC #modelling #performance
Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC’s (JPC, LMS, MC), pp. 396–400.
DATE-1999-LauwersG #estimation #performance
A Power Estimation Model for High-Speed CMOS A/D Converters (EL, GGEG), pp. 401–405.
DATE-1999-Nunez-AldanaV #effectiveness #performance #synthesis
An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis (ANA, RV), pp. 406–411.
DATE-1999-GuerraRRFR #fault #generative
An Accurate Error Control Mechanism for Simplification Before Generation Algorihms (OG, JDRG, ER, FVF, ÁRV), p. 412–?.
DATE-1999-FeldmanKL #modelling #performance
Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics (PF, SK, DEL), pp. 418–417.
DATE-1999-Troster #co-evolution #design #performance
Potentials of Chip-Package Co-Design for High-Speed Digital Applications (GT), pp. 423–422.
DATE-1999-WambacqDZEMB
A Single-Package Solution for Wireless Transceivers (PW, SD, HZ, ME, HDM, IB), p. 425–?.
DATE-1999-NicolaidisZ #online #scalability #testing
Scaling Deeper to Submicron: On-Line Testing to the Rescue (MN, YZ), p. 432–?.
DATE-1999-FournierAL #functional #product line #using #verification
Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors Family (LF, YA, ML), pp. 434–441.
DATE-1999-FerrandiFGS #functional #generative #specification
Symbolic Functional Vector Generation for VHDL Specifications (FF, FF, LG, DS), p. 442–?.
DATE-1999-TanS #diagrams #scalability #using
Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision Diagrams (XDT, CJRS), pp. 448–453.
DATE-1999-UbarRM #diagrams #simulation
Cycle-based Simulation with Decision Diagrams (RU, JR, AM), pp. 454–458.
DATE-1999-BuhlerPKB #approach #performance #process #simulation #using
Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel Approach (MB, MP, KK, UGB), p. 459–?.
DATE-1999-LinPR #fault
Full Scan Fault Coverage With Partial Scan (XL, IP, SMR), pp. 468–472.
DATE-1999-ShinKK #bound #multi #testing
At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System Clocks (JS, HK, SK), p. 473–?.
DATE-1999-ZhuG #design #named
OpenJ: An Extensible System Level Design Language (JZ, DG), pp. 480–484.
DATE-1999-HalambiGGKDN #architecture #compilation #named
EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator Retargetability (AH, PG, VG, AK, NDD, AN), pp. 485–490.
DATE-1999-RadetzkiSPN #analysis #data type #hardware #modelling #object-oriented #synthesis
Data Type Analysis for Hardware Synthesis from Object-Oriented Models (MR, AS, WPR, WN), p. 491–?.
DATE-1999-Holzheuer #analysis #how #process
How to use Knowledge in an Analysis Process (HH), pp. 498–502.
DATE-1999-RibasC #clustering #modelling
Digital MOS Circuit Partitioning with Symbolic Modeling (LR, JC), pp. 503–508.
DATE-1999-Montiel-NelsonNASN #design #logic #using
High Speed GaAs Subsystem Design using Feed Through Logic (JAMN, SN, VdA, RS, AN), p. 509–?.
DATE-1999-MillanEECC #logic #optimisation
Integrating Symbolic Techniques in ATPG-Based Sequential Logic Optimization (ESM, LE, JAE, SC, FC), pp. 516–520.
DATE-1999-MartinezAQH #algorithm #encoding #using
An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code Length (MM, MJA, JMQ, JLH), pp. 521–525.
DATE-1999-SilvaSM #algorithm #satisfiability
Algorithms for Solving Boolean Satisfiability in Combinational Circuits (LGeS, LMS, JPMS), pp. 526–530.
DATE-1999-StokSI
Wavefront Technology Mapping (LS, AJS, MAI), p. 531–?.
DATE-1999-StopjakovaMS #monitoring #testing
On-Chip Transient Current Monitor for Testing of Low Voltage CMOS IC (VS, HARM, MS), pp. 538–542.
DATE-1999-RiusF #energy #testing
Exploring the Combination of IDDQ and iDDt Testing: Energy Testing (JR, JF), pp. 543–548.
DATE-1999-SantosT #fault #simulation #using
Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDL (MBS, JPT), p. 549–?.
DATE-1999-VercauterenSV #constraints #generative #hardware #interface #realtime #synthesis
Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints (SV, JvdS, DV), pp. 556–561.
DATE-1999-ONilsJ #implementation #independence #operating system #protocol #specification #synthesis
Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol Specification (MO, AJ), pp. 562–567.
DATE-1999-ChangP #co-evolution #communication #design #named #programming #using
Codex-dp: Co-design of Communicating Systems Using Dynamic Programming (JMC, MP), p. 568–?.
DATE-1999-ToulouseBLN #3d #modelling #performance
Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense Layouts (AT, DB, CL, PN), pp. 576–580.
DATE-1999-NagC
Post-Placement Residual-Overlap Removal with Minimal Movement (SN, KC), pp. 581–586.
DATE-1999-KrupnovaS #clustering #multi
Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAs (HK, GS), p. 587–?.
DATE-1999-HamiltonOH
Self Recovering Controller and Datapath Codesign (SNH, AO, AH), pp. 596–601.
DATE-1999-EijkJMT #algorithm #identification #symmetry
Identification and Exploitation of Symmetries in DSP Algorithms (CAJvE, ETAFJ, BM, AHT), pp. 602–608.
DATE-1999-SantosJ #equivalence #on the fly
Exploiting State Equivalence on the Fly while Applying Code Motion and Speculation (LCVdS, JAGJ), p. 609–?.
DATE-1999-BolsensMDBV #hybrid #integration
Single Chip or Hybrid System Integration (IB, WM, LD, JB, HJMV), p. 616–?.
DATE-1999-RenovellPFZ #configuration management #interface #logic #testing
Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA’s (MR, JMP, JF, YZ), pp. 618–622.
DATE-1999-GoorN #evaluation #industrial #testing
Industrial Evaluation of DRAM Tests (AJvdG, JdN), pp. 623–630.
DATE-1999-TragoudasM #fault #functional #tool support
ATPG Tools for Delay Faults at the Functional Level (ST, MKM), p. 631–?.
DATE-1999-KallaC #equivalence #performance
Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence (PK, MJC), pp. 638–642.
DATE-1999-LiuPF
Minimizing Sensitivity to Delay Variations in High-Performance Synchronous Circuits (XL, MCP, EGF), pp. 643–649.
DATE-1999-EcklL #multi
Retiming Sequential Circuits with Multiple Register Classes (KE, CL), p. 650–?.
DATE-1999-YeCFCNC #design #verification
Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs (LY, FCC, PF, RC, NN, FC), pp. 658–663.
DATE-1999-WangYK #distributed #estimation
Coupled Noise Estimation for Distributed RC Interconnect Model (JMW, QY, ESK), pp. 664–668.
DATE-1999-Sheehan #reduction #using
Projective Convolution: RLC Model-Order Reduction Using the Impulse Response (BNS), p. 669–?.
DATE-1999-JacomePRL #design
The Design Space Layer: Supporting Early Design Space Exploration for Core-Based Designs (MFJ, HPP, AR, JCL), pp. 676–683.
DATE-1999-DalpassoBB #design #distributed #specification #validation
Specification and Validation of Distributed IP-Based Designs with JavaCAD (MD, AB, LB), pp. 684–688.
DATE-1999-BarnaR #object-oriented #reuse
Object-Oriented Reuse Methodology for VHDL (CB, WR), p. 689–?.
DATE-1999-JerrayaE #design #multi
Multi-Language System Design (AAJ, RE), p. 696–?.
DATE-1999-HellebrandWY #symmetry
Symmetric Transparent BIST for RAMs (SH, HJW, VNY), pp. 702–707.
DATE-1999-ZarrinehU #architecture #memory management #on the #programmable
On Programmable Memory Built-In Self Test Architectures (KZ, SJU), pp. 708–713.
DATE-1999-ChakrabortyGBKM #design #physics #self
A Physical Design Tool for Built-in Self-Repairable Static RAMs (KC, AG, MB, SK, PM), p. 714–?.
DATE-1999-NebelM #ada #c #java #question #specification
Java, VHDL-AMS, ADA or C for System Level Specifications? (WN, EM), p. 720.
DATE-1999-MoserN #case study #embedded
Case Study: System Model of Crane and Embedded Control (EM, WN), p. 721.
DATE-1999-AgaesseL #component
Virtual Components Application and Customization (JFA, BL), pp. 726–727.
DATE-1999-Haase #design
Design Methodology for IP Providers (JH), pp. 728–732.
DATE-1999-Dewilde #design #scalability #source code
Large European Programs in Microelectronic System and Circuit Design (PD), p. 734–?.
DATE-1999-RaikU #diagrams #generative #modelling #testing #using
Sequential Circuit Test Generation Using Decision Diagram Models (JR, RU), pp. 736–740.
DATE-1999-KonijnenburgLG #generative #identification #testing
Illegal State Space Identification for Sequential Circuit Test Generation (MHK, JTvdL, AJvdG), pp. 741–746.
DATE-1999-SantosoMRA #generative #named #testing #using
FreezeFrame: Compact Test Generation Using a Frozen Clock Strategy (YS, MCM, EMR, MA), p. 747–?.
DATE-1999-CornoRS #algorithm #approximate #equivalence #search-based #verification
Approximate Equivalence Verification of Sequential Circuits via Genetic Algorithms (FC, MSR, GS), pp. 754–755.
DATE-1999-StrehlT #diagrams #model checking #petri net
Interval Diagram Techniques for Symbolic Model Checking of Petri Nets (KS, LT), pp. 756–757.
DATE-1999-ThorntonWDD #diagrams #order #using
Variable Reordering for Shared Binary Decision Diagrams Using Output Probabilities (MAT, JPW, RD, ND), pp. 758–759.
DATE-1999-MeinelS #model checking #order #performance
Increasing Efficiency of Symbolic Model Checking by Accelerating Dynamic Variable Reordering (CM, CS), pp. 760–761.
DATE-1999-FornaciariSS #embedded #encoding
Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded Systems (WF, DS, CS), pp. 762–763.
DATE-1999-WeissSR #embedded #operating system #performance #realtime #using
Emulation of a Fast Reactive Embedded System using a Real Time Operating System (KW, TS, WR), pp. 764–765.
DATE-1999-MaestroMH #approach #hardware #problem
The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic Approach (JAM, DM, RH), pp. 766–767.
DATE-1999-FleischmannBK #component #configuration management #embedded #hardware #java
Codesign of Embedded Systems Based on Java and Reconfigurable Hardware Components (JF, KB, RK), pp. 768–769.
DATE-1999-MaamarR #adaptation #named #testing
ADOLT — An ADaptable On — Line Testing Scheme for VLSI Circuits (AM, GR), pp. 770–771.
DATE-1999-Kuchcinski #constraints #finite #graph #scheduling #using
Integrated Resource Assignment and Scheduling of Task Graphs Using Finite Domain Constraints (KK), pp. 772–773.
DATE-1999-PapachristouA #design #distributed
A Method of Distributed Controller Design for RTL Circuits (CAP, YA), pp. 774–775.
DATE-1999-ChoiB #array #design
OTA Amplifiers Design on Digital Sea-of-Transistors Array (JHC, SB), pp. 776–777.
DATE-1999-AlippiFPS #approach #configuration management #design
A DAG-Based Design Approach for Reconfigurable VLIW Processors (CA, WF, LP, MS), pp. 778–779.
DATE-1999-WuGR #approach #fault #performance #reduction
A Fault List Reduction Approach for Efficient Bridge Fault Diagnosis (JW, GSG, EMR), pp. 780–781.
DATE-1999-PasquierC #execution #realtime #simulation
An Object-Based Executable Model for Simulation of Real-Time Hw/Sw Systems (OP, JPC), pp. 782–783.
DATE-1999-ScherberM #flexibility #modelling #performance #simulation
An Efficient and Flexible Methodology for Modelling and Simulation of Heterogeneous Mechatronic Systems (SS, CMS), pp. 784–785.
DATE-1999-MaurerS #performance #simulation
Software Bit-Slicing: A Technique for Improving Simulation Performance (PMM, WJS), pp. 786–787.
DATE-1999-MartinolleDCF #user interface
Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI (FM, CD, DC, MF), pp. 788–789.
DATE-1999-DabrowskiP #case study #experience #modelling
Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL Technique (JD, AP), pp. 790–791.
DATE-1999-RayaneVN #detection #embedded
A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate Detection (IR, JVM, MN), p. 792–?.

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