Stem verilog$ (all stems)

31 papers:

DAC-2013-JangPK #simulation

An event-driven simulation methodology for integrated switching power supplies in SystemVerilog (JEJ, MJP, JK), p. 7.

DATE-2013-MiryalaMCMP #configuration management #logic

A verilog-a model for reconfigurable logic gates based on graphene pn-junctions (SM, MM, AC, EM, MP), pp. 877–880.

DATE-2011-KengSV #automation #debugging

Automated debugging of SystemVerilog assertions (BK, SS, AGV), pp. 323–328.

SEKE-2011-YooLJC #independence #named #source code

FBDtoVerilog: A Vendor-Independent Translation from FBDs into Verilog Programs (JY, JHL, SJ, SDC), pp. 48–51.

ASE-2010-DuleySK #algorithm #difference

A program differencing algorithm for verilog HDL (AD, CS, MK), pp. 477–486.

DATE-2010-RaffelsieperMS #library

Checking and deriving module paths in Verilog cell library descriptions (MR, MRM, CWHS), pp. 1506–1511.

PEPM-2009-SalamaMTGO #consistency #dependent type #using

Static consistency checking for verilog wire interconnects: using dependent types to check the sanity of verilog descriptions (CS, GM, WT, JG, JO), pp. 121–130.

DAC-2008-Cummings #design #verification

SystemVerilog implicit port enhancements accelerate system design & verification (CEC), pp. 231–236.

DAC-2008-Larson

Translation of an existing VMM-based SystemVerilog testbench to OVM (KDL), p. 237.

MSR-2008-SudakrishnanMWR #comprehension #debugging

Understanding bug fix patterns in verilog (SS, JTM, EJWJ, JR), pp. 39–42.

PEPM-2008-GillenwaterMSZTGO #hardware #static typing #using

Synthesizable high level hardware descriptions: using statically typed two-level languages to guarantee verilog synthesizability (JG, GM, CS, AYZ, WT, JG, JO), pp. 41–50.

SAC-2008-GruianW #architecture #case study #embedded #java

VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture (FG, MW), pp. 1492–1497.

DATE-2007-KroeningS #image #interactive #proving #refinement #using #word

Interactive presentation: Image computation and predicate refinement for RTL verilog using word level proofs (DK, NS), pp. 1325–1330.

DATE-2007-VermaHR #automation #behaviour #functional #generative #interactive #modelling

Interactive presentation: Automatic generation of functional coverage models from behavioral verilog descriptions (SV, IGH, KR), pp. 900–905.

TACAS-2007-JainKSC #abstraction #named #refinement

VCEGAR: Verilog CounterExample Guided Abstraction Refinement (HJ, DK, NS, EMC), pp. 583–586.

DATE-DF-2006-DasMDC #synthesis

Synthesis of system verilog assertions (SD, RM, PD, PPC), pp. 70–75.

CAV-2006-BustanH #complexity

Some Complexity Results for SystemVerilog Assertions (DB, JH), pp. 205–218.

DAC-2005-JainKSC #abstraction #refinement #verification #word

Word level predicate abstraction and refinement for verifying RTL verilog (HJ, DK, NS, EMC), pp. 445–450.

DAC-2004-AndrausS #abstraction #automation #modelling #verification

Automatic abstraction and verification of verilog models (ZSA, KAS), pp. 218–223.

DATE-v1-2004-BurnsSKY #synthesis #tool support #using

An Asynchronous Synthesis Toolset Using Verilog (FPB, DS, AK, AY), pp. 724–725.

DATE-v1-2004-SciutoMRSGFS #question

SystemC and SystemVerilog: Where do They Fit? Where are They Going? (DS, GM, WR, SS, FG, PF, JS), pp. 122–129.

DATE-v2-2004-Fitzpatric

System Verilog for VHDL Users (TF), pp. 1334–1341.

DAC-2003-ClarkeKY #behaviour #bound #c #consistency #model checking #source code #using

Behavioral consistency of C and verilog programs using bounded model checking (EMC, DK, KY), pp. 368–371.

DAC-2003-SaifhashemiP #abstraction #framework #modelling

Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction (AS, HP), pp. 330–333.

FME-2003-QinC #hardware

Mapping Statecharts to Verilog for Hardware/Software Co-specification (SQ, WNC), pp. 282–300.

IFM-2000-Bowen #animation #hardware #logic programming #semantics #specification

Combining Operational Semantics, Logic Programming and Literate Programming in the Specification and Animation of the Verilog Hardware Description Language (JPB), pp. 277–296.

DATE-1999-MartinolleDCF #user interface

Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUI (FM, CD, DC, MF), pp. 788–789.

DATE-1999-Sasaki #semantics #simulation #state machine

A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State Machine (HS), p. 353–?.

DAC-1997-XanthopoulosYC #architecture #case study #estimation #using

Architectural Exploration Using Verilog-Based Power Estimation: A Case Study of the IDCT (TX, YY, AC), pp. 415–420.

DAC-1996-Smith #c

VHDL & Verilog Compared & Contrasted — Plus Modeled Example Written in VHDL, Verilog and C (DJS), pp. 771–776.

LICS-1995-Gordon #challenge #semantics

The Semantic Challenge of Verilog HDL (MJCG), pp. 136–145.