Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
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Saraju P. Mohanty, Ramakrishna Velagapudi, Elias Kougianos
Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits
DATE, 2006.

DATE 2006
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@inproceedings{DATE-2006-MohantyVK,
	author        = "Saraju P. Mohanty and Ramakrishna Velagapudi and Elias Kougianos",
	booktitle     = "{Proceedings of the 10th Conference on Design, Automation and Test in Europe}",
	doi           = "10.1145/1131810",
	pages         = "1191--1196",
	publisher     = "{European Design and Automation Association, Leuven, Belgium}",
	title         = "{Physical-aware simulated annealing optimization of gate leakage in nanoscale datapath circuits}",
	year          = 2006,
}

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