Proceedings of the 19th International Symposium on High-Performance Computer Architecture
HPCA, 2013.

@proceedings{HPCA-2013,
	address       = "Shenzhen, China",
	ee            = "http://www.computer.org/csdl/proceedings/hpca/2013/5585/00/index.html",
	isbn          = "978-1-4673-5585-8",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the 19th International Symposium on High-Performance Computer Architecture}",
	year          = 2013,
}

Contents (55 items)

13 ×#named
12 ×#architecture
9 ×#memory management
8 ×#performance
7 ×#energy
5 ×#manycore
5 ×#using
4 ×#latency
4 ×#parallel
4 ×#predict

HPCA-2013-BlemMS #architecture

Power struggles: Revisiting the RISC vs. CISC debate on contemporary ARM and x86 architectures (ERB, JM, KS), pp. 1–12.

HPCA-2013-ZhuR #energy #mobile #web

High-performance and energy-efficient mobile web browsing on big/little systems (YZ, VJR), pp. 13–24.

HPCA-2013-LeeKH0 #power management

Skinflint DRAM system: Minimizing DRAM chip writes for low power (YL, SK, SH, JL), pp. 25–34.

HPCA-2013-LiZL #distributed #generative

Enabling distributed generation powered sustainable high-performance data center (CL, RZ, TL), pp. 35–46.

HPCA-2013-AframZG #implementation

A group-commit mechanism for ROB-based processors implementing the X86 ISA (FA, HZ, KG), pp. 47–58.

HPCA-2013-FarooqKJ #branch #compilation #predict

Store-Load-Branch (SLB) predictor: A compiler assisted branch prediction for data dependent branches (MUF, K, LKJ), pp. 59–70.

HPCA-2013-BonannoCLMPS #branch #predict

Two level bulk preload branch prediction (JB, AC, DL, UM, BP, AS), pp. 71–82.

HPCA-2013-ZebchukCTSM #named

RECAP: A region-based cure for the common cold (cache) (JZ, HWC, XT, VS, AM), pp. 83–94.

HPCA-2013-GuevaraLL #navigation

Navigating heterogeneous processors with market mechanisms (MG, BL, BCL), pp. 95–106.

HPCA-2013-DasAMKA #manycore #memory management #policy

Application-to-core mapping policies to reduce memory system interference in multi-core systems (RD, RA, OM, AK, MA), pp. 107–118.

HPCA-2013-KhanAWKJ #architecture #manycore #performance #using

Improving multi-core performance using mixed-cell cache architecture (SMK, ARA, CW, JK, DAJ), pp. 119–130.

HPCA-2013-BaekLNLK #capacity #effectiveness #named

ECM: Effective Capacity Maximizer for high-performance compressed caching (SB, HGL, CN, JL, JK), pp. 131–142.

HPCA-2013-ChangRLJ #comparison #energy #scalability

Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM (MTC, PR, SLL, BJ), pp. 143–154.

HPCA-2013-SandbergSHB #modelling #performance

Modeling performance variation due to cache sharing (AS, AS, EH, DBS), pp. 155–166.

HPCA-2013-SudanBLXMLB #architecture #lightweight #novel #using #web

A novel system architecture for web scale applications using lightweight CPUs and virtualized I/O (KS, SB, SL, MX, DM, GL, RB), pp. 167–178.

HPCA-2013-HouJZQDWGZ #effectiveness

Cost effective data center servers (RH, TJ, LZ, PQ, JD, HW, XG, SZ), pp. 179–187.

HPCA-2013-TangMZHHT #experience #optimisation

Optimizing Google’s warehouse scale computers: The NUMA experience (LT, JM, XZ, RH, RH, ET), pp. 188–197.

HPCA-2013-CarterABCDDFGGKLMMPTTVVX #architecture #named #ubiquitous

Runnemede: An architecture for Ubiquitous High-Performance Computing (NPC, AA, SB, RC, HD, DD, JBF, IG, RAG, RCK, RL, BM, AKM, WRP, JT, JT, NV, GV, JX), pp. 198–209.

HPCA-2013-LiZL13a #energy #interface #memory management

Exploring high-performance and energy proportional interface for phase change memory systems (ZL, RZ, TL), pp. 210–221.

HPCA-2013-JacobvitzCS #memory management

Coset coding to extend the lifetime of memory (ANJ, ARC, DJS), pp. 222–233.

HPCA-2013-WangDXJ #named

i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations (JW, XD, YX, NPJ), pp. 234–245.

HPCA-2013-XiaLC #architecture #physics #virtual machine

Architecture support for guest-transparent VM protection from untrusted hypervisor and physical attacks (YX, YL, HC), pp. 246–257.

HPCA-2013-KayaalpSNPA #architecture #named #reuse

SCRAP: Architecture for signature-based protection from Code Reuse Attacks (MK, TS, JN, DP, NBAG), pp. 258–269.

HPCA-2013-JianK #adaptation #reliability

Adaptive Reliability Chipkill Correct (ARCC) (XJ, RK), pp. 270–281.

HPCA-2013-YueZ #symmetry

Accelerating write by exploiting PCM asymmetries (JY, YZ), pp. 282–293.

HPCA-2013-CragoALP #energy #hybrid #latency #parallel #robust

Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processors (NCC, OA, SSL, SJP), pp. 294–305.

HPCA-2013-RaoWZX #manycore #optimisation #scheduling #virtual machine

Optimizing virtual machine scheduling in NUMA multicore systems (JR, KW, XZ, CZX), pp. 306–317.

HPCA-2013-SampsonYWCW #3d #parallel

Sonic Millip3De: A massively parallel 3D-stacked accelerator for 3D ultrasound (RS, MY, SW, CC, TFW), pp. 318–329.

HPCA-2013-GilaniKS #power management

Power-efficient computing for compute-intensive GPGPU applications (SZG, NSK, MJS), pp. 330–341.

HPCA-2013-GoswamiCL #architecture #memory management #throughput #using

Power-performance co-optimization of throughput core architecture using resistive memory (NG, BC, TL), pp. 342–353.

HPCA-2013-LustigM #cpu #fine-grained #gpu #latency

Reducing GPU offload latency via fine-grained CPU-GPU synchronization (DL, MM), pp. 354–365.

HPCA-2013-ChenP

Worm-Bubble Flow Control (LC, TMP), pp. 366–377.

HPCA-2013-KrishnaCKP #latency #using

Breaking the on-chip latency barrier using SMART (TK, CHOC, WCK, LSP), pp. 378–389.

HPCA-2013-ChangHPNXK #named #network

TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network (YYC, YSCH, MP, VN, YX, CTK), pp. 390–399.

HPCA-2013-AgrawalJAT #multi #named

Refrint: Intelligent refresh to minimize power in on-chip multiprocessor cache hierarchies (AA, PJ, AA, JT), pp. 400–411.

HPCA-2013-Abdel-MajeedA #performance

Warped register file: A power efficient register file for GPGPUs (MAM, MA), pp. 412–423.

HPCA-2013-HamCXL #energy #memory management

Disintegrated control for energy-efficient and heterogeneous memory systems (TJH, BKC, NX, BCL), pp. 424–435.

HPCA-2013-AnsariFGTM #lightweight #named

Illusionist: Transforming lightweight cores into aggressive cores on demand (AA, SF, SG, JT, SAM), pp. 436–447.

HPCA-2013-ArdestaniR #manycore #named #performance #using

ESESC: A fast multicore simulator using Time-Based Sampling (EKA, JR), pp. 448–459.

HPCA-2013-RobatmiliLEGSPBK #architecture #effectiveness #how #manycore #predict

How to implement effective prediction and forwarding for fusable dynamic multicore architectures (BR, DL, HE, MSSG, AS, AP, DB, SWK), pp. 460–471.

HPCA-2013-NereHLT #behaviour #biology #semantic gap

Bridging the semantic gap: Emulating biological neuronal behaviors with simple digital neurons (AN, AH, MHL, GT), pp. 472–483.

HPCA-2013-KoibuchiFMC #random

Layout-conscious random topologies for HPC off-chip interconnects (MK, IF, HM, HC), pp. 484–495.

HPCA-2013-AbeyratneDLSGDBM #scalability #symmetry #towards

Scaling towards kilo-core processors with asymmetric high-radix topologies (NA, RD, QL, KS, BG, RGD, DB, TNM), pp. 496–507.

HPCA-2013-SamihWKMTS #energy

Energy-efficient interconnect via Router Parking (AS, RW, AK, CM, TYCT, YS), pp. 508–519.

HPCA-2013-ZhaoCCD #memory management #transaction

In-network traffic regulation for Transactional Memory (LZ, WC, LC, JTD), pp. 520–531.

HPCA-2013-MahmoodKH #adaptation #architecture #named #scalability

Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling (TM, SK, SH), pp. 532–541.

HPCA-2013-KarpuzcuSKT #energy #named #towards

EnergySmart: Toward energy-efficient manycores for Near-Threshold Computing (URK, AAS, NSK, JT), pp. 542–553.

HPCA-2013-QianHSQ #dependence #memory management #named #parallel #performance

Rainbow: Efficient memory dependence recording with high replay parallelism for relaxed memory model (XQ, HH, BS, DQ), pp. 554–565.

HPCA-2013-BeuPHC #performance #verification

High-speed formal verification of heterogeneous coherence hierarchies (JGB, JAP, ERH, TMC), pp. 566–577.

HPCA-2013-SinghSFOA #architecture #gpu

Cache coherence for GPU architectures (IS, AS, WWLF, MO, TMA), pp. 578–590.

HPCA-2013-RhuE #control flow #execution #gpu #performance

The dual-path execution model for efficient GPU control flow (MR, ME), pp. 591–602.

HPCA-2013-WangCWMZLN #architecture #execution #parallel

A multiple SIMD, multiple data (MSMD) architecture: Parallel execution of dynamic and static SIMD fragments (YW, SC, JW, JM, KZ, WL, XN), pp. 603–614.

HPCA-2013-LeeKSLSM #architecture #latency #low cost

Tiered-latency DRAM: A low latency and low cost DRAM architecture (DL, YK, VS, JL, LS, OM), pp. 615–626.

HPCA-2013-NairCQ #memory management

A case for Refresh Pausing in DRAM memory systems (PJN, CCC, MKQ), pp. 627–638.

HPCA-2013-SubramanianSKJM #in memory #memory management #named #performance #predict

MISE: Providing performance predictability and improving fairness in shared main memory systems (LS, VS, YK, BJ, OM), pp. 639–650.