Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip
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Chifeng Wang, Nader Bagherzadeh
Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip
PDP, 2012.

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@inproceedings{PDP-2012-WangB,
	author        = "Chifeng Wang and Nader Bagherzadeh",
	booktitle     = "{Proceedings of the 20th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, PDP 2012, Munich, Germany, February 15-17, 2012}",
	doi           = "10.1109/PDP.2012.20",
	isbn          = "978-1-4673-0226-5",
	pages         = "457--464",
	publisher     = "{IEEE}",
	title         = "{Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip}",
	year          = 2012,
}

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