BibSLEIGH — Nader

Travelled to:

1 × France
3 × Germany
4 × USA

Collaborated with:

C.Wang W.Hu F.J.Kurdahi M.Sanchez-Elez M.Fernández S.E.Lee R.Hermida S.Wallace M.Gulati R.Maestre A.Khademzadeh M.Janidarmian R.Salamat M.Ebrahimi A.Demiriz A.Alhussien H.Du M.L.Anido H.Singh A.Eskandari J.Yang C.Chun C.Pan A.H.Kamalizad A.Koohi J.Liu P.H.Chou S.Azampanah R.Shojaee J.Davila A.d.Torres J.M.Sanchez F.Rivera N.Tabrizi G.Lu E.M.C.Filho M.Lee

Talks about:

chip (10) network (8) architectur (6) reconfigur (6) design (6) constraint (3) algorithm (3) schedul (3) morpho (3) applic (3)

Person: Nader Bagherzadeh

DBLP: Bagherzadeh:Nader

Contributed to:

2015

2013

2012

2011

2010

2006

2003

2002

2001

2000

1999

1997

1996

Wrote 19 papers:

PDP-2015-SalamatEB #3d #adaptation #algorithm #fault #strict: An Adaptive, Low Restrictive and Fault Resilient Routing Algorithm for 3D Network-on-Chip (RS, ME, NB), pp. 392–395.
PDP-2013-DemirizBA #architecture #constraints #design #named #programming #using: CPNoC: On Using Constraint Programming in Design of Network-on-Chip Architecture (AD, NB, AA), pp. 486–493.
PDP-2013-EskandariKBJ #algorithm #constraints #optimisation #quality #using: Quality of Service Optimization for Network-on-Chip Using Bandwidth-Constraint Mapping Algorithm (AE, AK, NB, MJ), pp. 504–508.
PDP-2012-AzampanahKBJS #adaptation #named #policy #tex: LATEX: New Selection Policy for Adaptive Routing in Application-Specific NoC (SA, AK, NB, MJ, RS), pp. 515–519.
PDP-2012-HuWB #analysis #design: Design and Analysis of a Mesh-based Wireless Network-on-Chip (WHH, CW, NB), pp. 483–490.
PDP-2012-WangB #architecture #design #evaluation #throughput: Design and Evaluation of a High Throughput QoS-Aware and Congestion-Aware Router Architecture for Network-on-Chip (CW, NB), pp. 457–464.
PDP-2011-WangHB #design #manycore: A Wireless Network-on-Chip Design for Multicore Platforms (CW, WHH, NB), pp. 409–416.
PDP-2011-YangCBL #framework #multi: Load Balancing for Data-Parallel Applications on Network-on-Chip Enabled Multi-processor Platform (JY, CC, NB, SEL), pp. 439–446.
PDP-2010-WangHLB #power management: Area and Power-efficient Innovative Network-on-Chip Architecurte (CW, WHH, SEL, NB), pp. 533–539.
DATE-DF-2006-DavilaTSSBR #algorithm #architecture #configuration management #design #implementation: Design and implementation of a rendering algorithm in a SIMD reconfigurable architecture (MorphoSys) (JD, AdT, JMS, MSE, NB, FR), pp. 52–57.
DATE-2003-DuSTBAF #configuration management #interactive: Interactive Ray Tracing on Reconfigurable SIMD MorphoSys (HD, MSE, NT, NB, MLA, MF), pp. 20144–20149.
DATE-2003-PanBKK #analysis #architecture #design #programmable: Design and Analysis of a Programmable Single-Chip Architecture for DVB-T Base-Band Receiver (CP, NB, AHK, AK), pp. 10468–10475.
DATE-2003-Sanchez-ElezFADBH #architecture #configuration management #data transformation #energy #memory management #multi: Low Energy Data Management for Different On-Chip Memory Levels in Multi-Context Reconfigurable Architectures (MSE, MF, MLA, HD, NB, RH), pp. 10036–10043.
DATE-2002-Sanchez-ElezFMMKHB #architecture #configuration management #multi: A Complete Data Scheduler for Multi-Context Reconfigurable Architectures (MSE, MF, RM, RH, NB, FJK), pp. 547–552.
DAC-2001-LiuCBK #constraints #embedded #power management #scheduling: Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems (JL, PHC, NB, FJK), pp. 840–845.
DAC-2000-SinghLFMLKB #case study #configuration management #multi #named: MorphoSys: case study of a reconfigurable computing system targeting multimedia applications (HS, GL, EMCF, RM, MHL, FJK, NB), pp. 573–578.
DATE-1999-MaestreKBSHF #configuration management #kernel #scheduling: Kernel Scheduling in Reconfigurable Computing (RM, FJK, NB, HS, RH, MF), pp. 90–96.
HPCA-1997-WallaceB #branch #multi #predict: Multiple Branch and Block Prediction (SW, NB), pp. 94–103.
HPCA-1996-GulatiB #parallel #performance #thread: Performance Study of a Multithreaded Superscalar Microprocessor (MG, NB), pp. 291–301.