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Travelled to:
1 × USA
Collaborated with:
∅
Talks about:
replac (1) design (1) comput (1) speed (1) simul (1) wire (1) rule (1) high (1)

Person: Adrian Hlynka

DBLP DBLP: Hlynka:Adrian

Contributed to:

DAC 19811981

Wrote 1 papers:

DAC-1981-Hlynka #design
A simulator to replace wire rules for high speed computer design (AH), pp. 113–117.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.