BibSLEIGH — Proceedings of the 18th Design Automation Conference

Robert J. Smith II
Proceedings of the 18th Design Automation Conference
DAC, 1981.

SYS

@proceedings{DAC-1981,
	acmid         = "800073",
	address       = "Nashville, Tennessee, USA",
	editor        = "Robert J. Smith II",
	publisher     = "{ACM/IEEE}",
	title         = "{Proceedings of the 18th Design Automation Conference}",
	year          = 1981,
}

Contents (132 items)

DAC-1981-Reitmeyer: CAD for military systems, an essential link to LSI, VLSI and VHSIC technology (RRJ), pp. 3–12.
DAC-1981-Eastman #design #representation: Recent developments in representation in the science of design (CME), pp. 13–21.
DAC-1981-PerskyES #automation #layout: The Hughes Automated Layout System — automated LSI/VLSI layout based on channel routing (GP, CE, DMS), pp. 22–28.
DAC-1981-Ji-GuangK #algorithm: An algorithm for searching shortest path by propagating wave fronts in four quadrants (XJG, TK), pp. 29–36.
DAC-1981-RothermelM #layout #power management: Computation of power supply nets in VLSI layout (HJR, DAM), pp. 37–42.
DAC-1981-Yamada #automation #design: Design automation status in Japan (AY), pp. 43–50.
DAC-1981-HosakaUM #automation #design: A design automation system for electronic switching systems (TH, KU, HM), pp. 51–58.
DAC-1981-TanakaMNOTK #array #design #logic: An integrated computer aided design system for gate array masterslices: Part 1. Logic reorganization system LORES-2 (CT, SM, SN, TO, MT, KK), pp. 59–65.
DAC-1981-Scoble #interactive #using: Creating and updating space occupancy and building plans using interactive graphics (RAS), pp. 66–73.
DAC-1981-Kalay #generative #interactive #testing: Interactive shape generation and spatial conflict testing (YEK), pp. 75–81.
DAC-1981-Cory #functional #simulation #verification: Symbolic simulation for functional verification with ADLIB and SDL (WEC), pp. 82–89.
DAC-1981-McFarland #automation #correctness #design #on the #optimisation #proving: On proving the correctness of optimizing transformations in a digital design automation system (MCM), pp. 90–97.
DAC-1981-Wojtkowiak #design #functional #specification: Deterministic systems design from functional specifications (HW), pp. 98–104.
DAC-1981-SasakiYAHKS #design #scalability #verification: Hierarchical design verification for large digital systems (TS, AY, TA, KH, SK, SS), pp. 105–112.
DAC-1981-Hlynka #design: A simulator to replace wire rules for high speed computer design (AH), pp. 113–117.
DAC-1981-KamikawaiYCFT: A critical path delay check system (RK, MY, TC, KF, YT), pp. 118–123.
DAC-1981-Ruehli #analysis #logic #modelling #overview #scalability #simulation: Survey of analysis, simulation and modeling for large scale logic circuits (AER), pp. 124–129.
DAC-1981-AranoffA: Routing of printed circuit boards (SA, YA), pp. 130–136.
DAC-1981-Akers #algorithm #linear #on the #using: On the use of the linear assignment algorithm in module placement (SBA), pp. 137–144.
DAC-1981-Shupe #automation #component #interactive: Automatic component placement in an interactive minicomputer environment (CFS), pp. 145–152.
DAC-1981-OdawaraIIK #automation #named: PAS-LOP: An automatic module location system for PWB (GO, KI, NI, TK), pp. 153–159.
DAC-1981-Mills #approach #design: A totally integrated systems approach to design and manufacturing at McDonnell Douglas Corporation (MM), pp. 160–165.
DAC-1981-Curl #automation #design: Mechanical design automation in IBM Poughkeepsie (GWCJ), pp. 166–170.
DAC-1981-DewhirstH #analysis #design #modelling: Application of volumetric modeling to mechanical design and analysis (DLD, RCH), pp. 171–178.
DAC-1981-Chan: A perspective view of the MODCON system (YKC), pp. 179–188.
DAC-1981-Abramovici #algorithm #testing: A maximal resolution guided-probe testing algorithm (MA), pp. 189–195.
DAC-1981-AgrawalSA #fault #quality: LSI product quality and fault coverage (VDA, SCS, PA), pp. 196–203.
DAC-1981-Masurkar #algorithm #development #fault #identification #network: An algorithmic pretest development for fault identification in analog networks (VM), pp. 204–212.
DAC-1981-BellonSG #hardware: Hardware description levels and test for complex circuits (CB, GS, JMG), pp. 213–219.
DAC-1981-LeeCJ #automation #generative: Automatic generation and characterization of CMOS polycells (CML, BRC, SJ), pp. 220–224.
DAC-1981-Weste #grid #layout: Virtual grid symbolic layout (NW), pp. 225–233.
DAC-1981-Trimberger #interactive #layout: Combining graphics and a layout language in a single interactive system (ST), pp. 234–239.
DAC-1981-FrancoR #design: The Cell Design System (DF, LR), pp. 240–247.
DAC-1981-HirschhornHB #algorithm #data type #functional #simulation: Functional level simulation in FANSIM3 — algorithms, data structures and results (SH, MH, CB), pp. 248–255.
DAC-1981-GoshimaOKMTO #logic #scalability: Diagnostic system for large scale logic cards and LSIs (SG, YO, TK, TM, YT, YO), pp. 256–259.
DAC-1981-GoelR #automation #generative #logic #named #testing: PODEM-X: An automatic test generation system for VLSI logic structures (PG, BCR), pp. 260–268.
DAC-1981-BreuerP #roadmap #simulation: Digital system simulation: Current status and future trends or darwin’s theory of simulation (MAB, ACP), pp. 269–275.
DAC-1981-HoltS #design #specification: BOLT-a block oriented design specification language (DH, SS), pp. 276–279.
DAC-1981-HoltH #logic: A MOS/LSI oriented logic simulator (DH, DH), pp. 280–287.
DAC-1981-NgGK #parametricity #verification: A timing verification system based on extracted MOS/VLSI circuit parameters (PN, WG, RK), pp. 288–292.
DAC-1981-HorngL #automation #interactive #layout: An automatic/interactive layout planning system for arbitrarily-sized rectangular building blocks (CSH, ML), pp. 293–300.
DAC-1981-Brown #state machine: A State-Machine Synthesizer — SMS (DWB), pp. 301–305.
DAC-1981-BilgoryG #automation #generative: Automatic generation of cells for recurrence structures (AB, DDG), pp. 306–313.
DAC-1981-AtkinsLO #design #overview: Overview of an Arithmetic Design System (DEA, WL, SO), pp. 314–321.
DAC-1981-GoatesP #array #design #layout #lisp #logic #modelling #named: ABLE: A LISP-based layout modeling language with user-definable procedural models for storage/logic array design (GBG, SSP), pp. 322–329.
DAC-1981-Dutton #automation #design #perspective #tool support: Position statement — tools for design automation from a university point of view (RWD), p. 333.
DAC-1981-Gould #automation #design: Changing the Government’s role in design automation (JMG), pp. 334–335.
DAC-1981-Gwyn: Government interest and involvement in DA from the Sandia viewpoint (CWG), p. 336.
DAC-1981-Losleben #roadmap: Current issues in government interest and involvement in CAD (PL), pp. 337–341.
DAC-1981-Nash: Government actions to increase CAD software productivity (DCN), p. 342.
DAC-1981-Spence #automation #design #perspective: Design Automation — a perspective (HWS), p. 343.
DAC-1981-Sumney #automation #design #development #perspective: Government interest and involvement in design automation development the VHSIC perspective (LWS), pp. 344–346.
DAC-1981-El-Ziq #automation #fault #generative #testing: Automatic test generation for stuck-open faults in CMOS VLSI (YMEZ), pp. 347–354.
DAC-1981-AlmyR #fault #using: Using error latch trace to obtain diagnostic information (PMA, JLR), pp. 355–359.
DAC-1981-McDermott #analysis #fault #random: Random fault analysis (RMM), pp. 360–364.
DAC-1981-BradyS #layout #optimisation #verification: Verification and optimization for LSI & PCB layout (HNB, RJSI), pp. 365–371.
DAC-1981-TsuiS #multi: A high-density multilayer PCB router based on necessary and sufficient conditions for single row routing (RYT, RJSI), pp. 372–381.
DAC-1981-DeesS #performance: Performance of interconnection rip-up and reroute strategies (WADJ, RJSI), pp. 382–390.
DAC-1981-KangC #automation #synthesis: Automatic PLA synthesis from a DDL-P description (SK, WMvC), pp. 391–397.
DAC-1981-SuwaK: A computer-aided-design system for segmented-folded PLA macro-cells (IS, WJK), pp. 398–405.
DAC-1981-Paillotin #optimisation: Optimization of the PLA area (JFP), pp. 406–410.
DAC-1981-PatelC #clustering #problem: Partitioning for VLSI placement problems (AMP, LCC), pp. 411–418.
DAC-1981-MalladiSV #automation: Automatic placement of rectangular blocks with the interconnection channels (RM, GS, AV), pp. 419–425.
DAC-1981-KhokhaniPFSH: Placement of variable size circuits on LSI masterslices (KHK, AMP, WF, JS, DH), pp. 426–434.
DAC-1981-SakauyeLRETSABW #design #set #source code: A set of programs for MOS design (GS, AL, JR, RE, JT, ESYS, EA, FB, PSW), pp. 435–442.
DAC-1981-OdawaraKAK #design #interactive #logic #named: PAS-CIP: An interactive logic design system (GO, SK, HA, YK), pp. 443–450.
DAC-1981-SaitoUK #design #logic: A CAD system for logic design based on frames and demons (TS, TU, NK), pp. 451–456.
DAC-1981-Goldstein #bound: Defining the bounding edges of a SynthaVision solid model (RCG), pp. 457–461.
DAC-1981-Luts #geometry #modelling: Geometric modeling technology (WL), p. 462.
DAC-1981-WolfeFG #interactive #modelling: Interactive graphics for volume modeling (RNW, WJF, FG), pp. 463–470.
DAC-1981-TsengS #modelling #synthesis: The modeling and synthesis of bus systems (CJT, DPS), pp. 471–478.
DAC-1981-LeiveT #logic #synthesis: A technology relative Logic Synthesis and Module Selection system (GWL, DET), pp. 479–485.
DAC-1981-NagleP #algorithm #design #hardware #multi: Algorithms for multiple-criterion design of microprogrammed control hardware (AWN, ACP), pp. 486–493.
DAC-1981-Anderson #design #interactive #multi: A multiprocessor raster display for interactive graphics system design (WMA), pp. 494–497.
DAC-1981-Ramsay #array #design #logic: A remote design station for customer Uncommitted Logic Array designs (FRR), pp. 498–504.
DAC-1981-EdmondsonJ #layout #low cost #verification: A low cost hierarchical system for VLSI layout and verification (THE, RMJ), pp. 505–510.
DAC-1981-Leinwand #logic #process #simulation: Process oriented logic simulation (SML), pp. 511–517.
DAC-1981-ArmstrongD #logic #named: GSP: A logic simulator for LSI (JRA, DED), pp. 518–524.
DAC-1981-Krohn #simulation: Vector coding techniques for high speed digital simulation (HEK), pp. 525–529.
DAC-1981-NashW #design #development #re-engineering: Software engineering applied to computer-aided design (CAD) software development (DCN, HW), pp. 530–539.
DAC-1981-Wong #design: Computer-aided computer-aided design: Improving CAD programmer productivity (SW), pp. 540–545.
DAC-1981-BatiniL #concept #database #design #interactive #named: INCOD: A system for Interactive Conceptual Data Base Design (CB, ML), pp. 546–554.
DAC-1981-Lauther #algorithm: An O (N log N) algorithm for Boolean mask operations (UL), pp. 555–562.
DAC-1981-KozawaTSMI #algorithm #concurrent: A concurrent pattern operation algorithm for VLSI mask data (TK, AT, JS, CM, TI), pp. 563–570.
DAC-1981-Wilmore #performance: Efficient Boolean operations on IC masks (JAW), pp. 571–579.
DAC-1981-McDermott81a #design #process: Domain knowledge and the design process (JM), pp. 580–588.
DAC-1981-Zintl #database: A CODASYL CAD data base system (GZ), pp. 589–594.
DAC-1981-RobertsBJ #database #design: A vertically organized computer-aided design data base (KAR, TEB, DHJ), pp. 595–602.
DAC-1981-Glasser #behaviour: The analog behavior of digital integrated circuits (LAG), pp. 603–612.
DAC-1981-PenfieldR #network: Signal delay in RC tree networks (PPJ, JR), pp. 613–617.
DAC-1981-Lerman #automation #design #generative #integration: The generation of Technical Data Drawing Packages by the integration of Design Automation Graphics (HNL), pp. 618–622.
DAC-1981-SimsC #automation #design #documentation: User documentation for Design Automation at TI (DMS, JC), pp. 623–631.
DAC-1981-Cleghorn #design #named: PRIMEAIDS: An integrated electrical design environment (RC), pp. 632–638.
DAC-1981-IshiiIIYK #automation #diagrams #editing #interactive #logic: Automatic input and interactive editing systems of logic circuit diagrams (MI, YI, MI, MY, SK), pp. 639–645.
DAC-1981-Haynie #automation #database #design #hybrid #network #relational: The relational/network Hybrid data model for Design Automation Databases (MNH), pp. 646–652.
DAC-1981-LacroixP #data type: Data structures for CAD object description (ML, AP), pp. 653–659.
DAC-1981-WallaceH #probability: Some properties of a probabilistic model for global wiring (DW, LH), pp. 660–667.
DAC-1981-Heinisch: Aiming at a general routing strategy (JH), pp. 668–675.
DAC-1981-Heller #design #physics: Contrasts in physical design between LSI and VLSI (WRH), pp. 676–683.
DAC-1981-AblasserJ #layout #recognition #verification: Circuit recognition and verification based on layout information (IA, UJ), pp. 684–689.
DAC-1981-YoshidaOG #named #verification: PANAMAP-B: A mask verification system for bipolar IC (JY, TO, YG), pp. 690–695.
DAC-1981-Corbin: Custom VLSI electrical rule checking in an intelligent terminal (LVC), pp. 696–701.
DAC-1981-McNallD #approach: A structured approach to selecting a CAD/CAM system (RIMJ, RJD), p. 702.
DAC-1981-PeledC #design: The “gap” between users and designers of CAD/CAM systems: Search for solutions (JP, MPC), pp. 703–705.
DAC-1981-Barck #automation #evolution #interface: The role of engineering in the evolving technology/automation interface (PEB), pp. 706–707.
DAC-1981-Burdick #design #formal method #process #what: What to do when the seat of your pants wears out — the formalization of the VLSI design process (EB), pp. 708–709.
DAC-1981-Felton: The effects of CAD on the engineering organization (PF), pp. 710–711.
DAC-1981-Lydick #automation #evolution #interface: The role of engineering in the evolving technology/automation interface (RPL), p. 712.
DAC-1981-Lambert #design #physics: Graphics language / one — IBM Corporate-Wide physical design data format (DRL), pp. 713–719.
DAC-1981-Ward #verification: A total verification of printed circuit artwork (MAW), pp. 720–725.
DAC-1981-Williams #automation #layout #verification: Automatic VLSI layout verification (LW), pp. 726–732.
DAC-1981-CiesielskiK: An optimum layer assignment for routing in ICs and PCBs (MJC, EK), pp. 733–737.
DAC-1981-TsukiyamaKS #multi #on the #problem: On the layering problem of multilayer PWB wiring (ST, ESK, IS), pp. 738–745.
DAC-1981-DoreauK #algorithm #named: TWIGY — a topological algorithm based routing system (MTD, PK), pp. 746–755.
DAC-1981-YoungC #preprocessor: A preprocessor for channel routing (MHY, LC), pp. 756–761.
DAC-1981-Wada: A dogleg “optimal” channel router with completion enhancements (MMW), pp. 762–768.
DAC-1981-Suen #estimation #statistics: A statistical model for net length estimation (LCS), pp. 769–774.
DAC-1981-Sherwood #logic #modelling #simulation: A MOS modelling technique for 4-state true-value hierarchical logic simulation or Karnough knowledge (WS), pp. 775–785.
DAC-1981-Bryant #named: MOSSIM: A switch-level simulator for MOS LSI (REB), pp. 786–790.
DAC-1981-RaethALB #functional #logic #modelling #simulation: Functional modelling for logic simulation (PGR, JMA, GBL, JMB), pp. 791–795.
DAC-1981-EllenbergerN #architecture #design #named: AIDE — a tool for computer architecture design (DJE, YWN), pp. 796–803.
DAC-1981-MartinBLMMTW #design #named #problem: CELTIC — solving the problems of LSI design with an integrated polycell DA system (GM, JB, TL, DM, JM, DT, LW), pp. 804–811.
DAC-1981-TanakaMTYOTKT #array #design #layout: An integrated computer aided design system for gate array masterslices: Part 2 the layout design system MARS-M3 (CT, SM, HT, TY, KO, MT, RK, MT), pp. 812–819.
DAC-1981-ChibaOKNIK #layout #named: SHARPS: A hierarchical layout system for VLSI (TC, NO, TK, IN, TI, SK), pp. 820–827.
DAC-1981-SatoNTSOY #layout #named: MILD — A cell-based layout system for MOS-LSI (KS, TN, MT, HS, MO, TY), pp. 828–836.
DAC-1981-BlankSC #algorithm #architecture #parallel: A parallel bit map processor architecture for DA algorithms (TB, MS, WMvC), pp. 837–845.
DAC-1981-HaferP #analysis #design #formal method #logic #specification: A formal method for the specification, analysis, and design of register-transfer level digital logic (LJH, ACP), pp. 846–853.
DAC-1981-Berman #comparison #logic #on the: On logic comparison (LB), pp. 854–861.
DAC-1981-Montoye #performance: Area-time efficient addition in charge based technology (RKM), pp. 862–872.
DAC-1981-Bergsten #assembly #design: Computer-Aided Design, Manufacturing, Assembly and Test (CADMAT) (FCB), pp. 873–880.
DAC-1981-SoleckyP #testing #verification: Test data verification — not just the final step for test data before release for production testing (PS, RLP), pp. 881–890.
DAC-1981-HsuSB #fault #testing: Structured trace diagnosis for LSSD board testing — an alternative to full fault simulated diagnosis (FCH, PS, REB), pp. 891–897.

Robert J. Smith IIProceedings of the 18th Design Automation ConferenceDAC, 1981.

Contents (132 items)

Robert J. Smith II
Proceedings of the 18th Design Automation Conference
DAC, 1981.