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Collaborated with:
J.Reineke
Talks about:
microarchitectur (1) throughput (1) character (1) instruct (1) latenc (1) intel (1) usag (1) port (1) info (1) uop (1)

Person: Andreas Abel 0002

DBLP DBLP: 0002:Andreas_Abel

Contributed to:

ASPLOS 20192019

Wrote 1 papers:

ASPLOS-2019-0002R #architecture #latency #throughput
uops.info: Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures (AA0, JR), pp. 673–686.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.