BibSLEIGH — instruct stem

Used together with:

set (74)
processor (51)
base (49)
schedul (43)
system (33)

Stem instruct$ (all stems)

388 papers:

DAC-2015-EspinosaHAAR #analysis #correlation #robust #set #verification: Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification (JE, CH, JA, DdA, JCR), p. 6.
DATE-2015-ConstantinWKCB: Exploiting dynamic timing margins in microprocessors for frequency-over-scaling with instruction-based clock adjustment (JC, LW, GK, AC, AB), pp. 381–386.
ITiCSE-2015-MuibiDP #design #education #web: Teacher Perspectives on Web Design Instruction (HM, BD, THP), pp. 231–236.
ITiCSE-2015-PalI #programming: Classroom Versus Screencast for Native Language Learners: Effect of Medium of Instruction on Knowledge of Programming (YP, SI), pp. 290–295.
CHI-2015-ORourkeAGP #automation #framework #generative #interactive: A Framework for Automatically Generating Interactive Instructional Scaffolding (EO, EA, SG, ZP), pp. 1545–1554.
DHM-HM-2015-KikuchiSZTGH #quantifier: Effects of Quantified Instructional Tool on Spray-up Fabrication Method (TK, ES, YZ, YT, AG, HH), pp. 104–113.
DUXU-UI-2015-SpinilloP #design #interactive #visual notation: An Interactive Guide to Design Animated Visual Instructions in Brazil (CGS, RP), pp. 374–381.
HIMI-IKC-2015-NakamuraTA #design #student: Proposal of an Instructional Design Support System Based on Consensus Among Academic Staff and Students (SN, TT, TA), pp. 370–377.
LCT-2015-HasegawaSSHSO #comprehension #gesture: The Effect of Metaphoric Gestures on Schematic Understanding of Instruction Performed by a Pedagogical Conversational Agent (DH, SS, NS, TH, HS, KO), pp. 361–371.
LCT-2015-RiveiroDKJB: Supporting Golf Coaching and Swing Instruction with Computer-Based Training Systems (MR, AD, RK, UJ, PB), pp. 279–290.
LCT-2015-TriantafyllouT #student: Out of Classroom Instruction in the Flipped Classroom: The Tough Task of Engaging the Students (ET, OT), pp. 714–723.
ASE-2014-PalepuJ #dynamic analysis #slicing: Discriminating influences among instructions in a dynamic slice (VKP, JAJ), pp. 37–42.
CASE-2014-WangFZL #artificial reality #collaboration #maintenance: An augmented reality based system for remote collaborative maintenance instruction of complex products (JW, YF, CZ, SL), pp. 309–314.
DAC-2014-KleebergerMS #analysis: Workload- and Instruction-Aware Timing Analysis: The missing Link between Technology and System-level Resilience (VK, PRM, US), p. 6.
DATE-2014-DingLM: WCET-Centric dynamic instruction cache locking (HD, YL, TM), pp. 1–6.
DATE-2014-KamalGAP #approximate #performance #using: Improving efficiency of extensible processors by using approximate custom instructions (MK, AG, AAK, MP), pp. 1–4.
DATE-2014-KimH #automation #generative #parallel: Automatic generation of custom SIMD instructions for Superword Level Parallelism (TK, YH), pp. 1–6.
DATE-2014-TsoutsosM #named: HEROIC: Homomorphically EncRypted One Instruction Computer (NGT, MM), pp. 1–6.
SIGMOD-2014-ArnoldHFSKL #database #set: An application-specific instruction set for accelerating set-oriented database primitives (OA, SH, GF, BS, TK, WL), pp. 767–778.
VLDB-2014-TozunAAM #named #transaction: ADDICT: Advanced Instruction Chasing for Transactions (PT, IA, AA, AM), pp. 1893–1904.
VLDB-2015-InoueOT14 #branch #performance #predict #set: Faster Set Intersection with SIMD instructions by Reducing Branch Mispredictions (HI, MO, KT), pp. 293–304.
ITiCSE-2014-ZingaroP: Peer instruction: a link to the exam (DZ, LP), pp. 255–260.
CHI-2014-KizilcecPS #video #visual notation: Showing face in video instruction: effects on information retention, visual attention, and affect (RFK, KP, LS), pp. 2095–2102.
CHI-2014-MentisCS #learning: Learning to see the body: supporting instructional practices in laparoscopic surgical procedures (HMM, AC, SDS), pp. 2113–2122.
DHM-2014-IkenoboKKTG #classification: The Classification Tendency and Common Denomination of the Points Paid Attention in Ikebana Instruction (YI, NK, NK, YT, AG), pp. 263–272.
HCI-AIMT-2014-RestyanditoCP: The Effect of Voice Instruction on the Construction of Mental Model (R, AHSC, UP), pp. 481–491.
HPCA-2014-FytrakiVKFG #monitoring #named #programmable: FADE: A programmable filtering accelerator for instruction-grain monitoring (SF, EV, YOK, BF, BG), pp. 108–119.
LCTES-2014-ZhengW #named: WCET: aware dynamic instruction cache locking (WZ, HW), pp. 53–62.
DAC-2013-DingLM #analysis #multi #realtime: Integrated instruction cache analysis and locking in multitasking real-time systems (HD, YL, TM), p. 10.
DAC-2013-WagstaffGFT #architecture #partial evaluation #set: Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture description (HW, MG, BF, NPT), p. 6.
DATE-2013-AnanthanarayananGP #detection #fault #low cost #set #using: Low cost permanent fault detection using ultra-reduced instruction set co-processors (SA, SG, HDP), pp. 933–938.
DATE-2013-Hara-AzumiFKT #process: Instruction-set extension under process variation and aging effects (YHA, FF, SK, MBT), pp. 182–187.
DATE-2013-LiSRRRAHP #configuration management #named: CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors (TL, MS, SR, SR, RGR, JAA, JH, SP), pp. 707–712.
DATE-2013-YuZHWLT #approach #manycore #set #simulation: A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations (FWY, BHZ, YHH, HIW, CRL, RST), pp. 643–648.
ITiCSE-2013-PorterGGMT: Peer instruction in computer science at small liberal arts colleges (LP, SG, JG, AM, CT), pp. 129–134.
WCRE-2013-ClearyGVSSP #analysis #interactive #memory management #multi: Reconstructing program memory state from multi-gigabyte instruction traces to support interactive analysis (BC, PG, EV, MADS, MS, FP), pp. 42–51.
ICFP-2013-MainlandLJ: Exploiting vector instructions with generalized stream fusio (GM, RL, SLPJ), pp. 37–48.
CHI-2013-McDonaldP #testing: The effect of global instructions on think-aloud testing (SM, HP), pp. 2941–2944.
DHM-HB-2013-SchmuntzschYR #industrial #modelling: Combining Motion Capture and Digital Human Modeling for Creating Instructions in Industrial Settings (US, UY, MR), pp. 124–133.
DUXU-WM-2013-SpinilloS #comprehension #usability: Beyond Comprehension: A Usability Study on User Instruction Manual for Stove with Steam Function (CGS, KCASS), pp. 441–449.
ICEIS-v2-2013-ClayerTC #adaptation #approach #design #education #towards: Towards a Pattern-based Adaptive Approach for Instructional Design based on Teacher’s Pedagogical Design Scheme (JPC, CT, CC), pp. 532–538.
KEOD-2013-JiC: From Structured Task Instructions to Robot Task Plans (JJ, XC), pp. 237–244.
SAC-2013-XuTTZ #approach #fault #fine-grained: An instruction-level fine-grained recovery approach for soft errors (JX, QT, LT, HZ), pp. 1511–1516.
LCTES-2013-FinlaysonDGUWST #performance #pipes and filters: Improving processor efficiency by statically pipelining instructions (IF, BD, PG, GRU, DBW, MS, GST), pp. 33–44.
LCTES-2013-PorpodasC #adaptation #clustering #named #scheduling: LUCAS: latency-adaptive unified cluster assignment and instruction scheduling (VP, MC), pp. 45–54.
CASE-2012-YamamotoD #interface #learning: Robot interface learning user-defined voice instructions (DY, MD), pp. 926–929.
DAC-2012-ChatterjeeKMZB #architecture: Checking architectural outputs instruction-by-instruction on acceleration platforms (DC, AK, RM, AZ, VB), pp. 955–961.
DAC-2012-DingLM: WCET-centric partial instruction cache locking (HD, YL, TM), pp. 412–420.
DAC-2012-RajendiranAPTG #reliability #set: Reliable computing with ultra-reduced instruction set co-processors (AR, SA, HDP, MVT, SG), pp. 697–702.
DAC-2012-RehmanSH #compilation #scheduling: Instruction scheduling for reliability-aware compilation (SR, MS, JH), pp. 1292–1300.
DAC-2012-RoyC #analysis #predict: Predicting timing violations through instruction-level path sensitization analysis (SR, KC), pp. 1074–1081.
DATE-2012-KatzRZ #csp #generative #using: Generating instruction streams using abstract CSP (YK, MR, AZ), pp. 15–20.
DATE-2012-PrakashP #architecture #memory management #precise: An instruction scratchpad memory allocation for the precision timed architecture (AP, HDP), pp. 659–664.
DATE-2012-RahimiBG #analysis: Analysis of instruction-level vulnerability to dynamic voltage and temperature variations (AR, LB, RKG), pp. 1102–1105.
DATE-2012-ThachTKI #estimation #performance: Fast cycle estimation methodology for instruction-level emulator (DT, YT, SK, AI), pp. 248–251.
ITiCSE-2012-CamaraPV #collaboration #evaluation #framework #learning #programming: Evaluation of a collaborative instructional framework for programming learning (LMSC, MPV, JÁVI), pp. 162–167.
SCAM-2012-MurakamiHHIK #clone detection #detection: Folding Repeated Instructions for Improving Token-Based Code Clone Detection (HM, KH, YH, HI, SK), pp. 64–73.
PLDI-2012-GodefroidT #automation #encoding #synthesis: Automated synthesis of symbolic instruction encodings from I/O samples (PG, AT), pp. 441–452.
CHI-2012-BruunS #testing #usability: The effect of task assignments and instruction types on remote asynchronous usability testing (AB, JS), pp. 2117–2126.
CHI-2012-FothergillMKN #gesture #interactive #people: Instructing people for training gestural interactive systems (SF, HMM, PK, SN), pp. 1737–1746.
CHI-2012-TolmieBFBATFG #case study #experience #quote: “Act natural”: instructions, compliance and accountability in ambulatory experiences (PT, SB, MF, PB, MA, NT, JRF, GG), pp. 1519–1528.
SIGIR-2012-WebberTD: Effect of written instructions on assessor agreement (WW, BT, MD), pp. 1053–1054.
REFSQ-2012-Adam #elicitation #product line #requirements: Providing Software Product Line Knowledge to Requirements Engineers — A Template for Elicitation Instructions (SA), pp. 147–164.
CGO-2012-MurrayF #automation #compilation #set: Compiling for automatically generated instruction set extensions (ACM, BF), pp. 13–22.
CGO-2012-PlazarKMF: WCET-aware static locking of instruction caches (SP, JCK, PM, HF), pp. 44–52.
LCTES-2012-KyleBFLT #embedded #manycore #set #simulation #using: Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation (SCK, IB, BF, HL, NPT), pp. 21–30.
DAC-2011-WuWFT #distributed #manycore #scheduling #simulation: A high-parallelism distributed scheduling mechanism for multi-core instruction-set simulation (MHW, PCW, CYF, RST), pp. 339–344.
DATE-2011-AhmedSBH #configuration management #multi #named #runtime: mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions (WA, MS, LB, JH), pp. 1554–1559.
DATE-2011-KamalAP: Timing variation-aware custom instruction extension technique (MK, AAK, MP), pp. 1517–1520.
DATE-2011-MichelFP #embedded #simulation: Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation (LM, NF, FP), pp. 277–280.
CSEET-2011-GannodABB #communication #education #integration #question #re-engineering: Is integration of communication and technical instruction across the SE curriculum a viable strategy for improving the real-world communication abilities of software engineering graduates? (GCG, PVA, JEB, AB), pp. 525–529.
CSEET-2011-MonteithM #student: Integrating instructional and study materials to tailor a student-specific resource (JYM, JDM), pp. 294–303.
ITiCSE-2011-PorterLSCZ #case study #experience #multi: Experience report: a multi-classroom report on the value of peer instruction (LP, CBL, BS, QIC, DZ), pp. 138–142.
ITiCSE-2011-RossF #3d #experience: STEM and ICT instructional worlds: the 3d experience (KR, YF), p. 381.
HCI-UA-2011-OhkawaM #development: A Development of Web-Based Player for Instructions Recorded with the Electronic Blackboard System IMPRESSION (YO, TM), pp. 500–509.
HIMI-v1-2011-TakeuchiN #how #question: How Do Real or Virtual Agent’s Body and Instructions Contribute to Task Achievement? (YT, HN), pp. 142–151.
POPL-2011-RamseyD #composition #dependent type #independence #low level #type system #using: Resourceable, retargetable, modular instruction selection using a machine-independent, type-based tiling of low-level intermediate code (NR, JD), pp. 575–586.
SAC-2011-LiuZ11a #analysis #distance #performance #stack #worst-case: Stack distance based worst-case instruction cache performance analysis (YL, WZ), pp. 723–728.
CC-2011-Brunthaler #interpreter #scheduling: Interpreter Instruction Scheduling (SB), pp. 164–178.
CGO-2011-JonesBMC #optimisation #performance: Link-time optimization for power efficiency in a tagless instruction cache (TMJ, SB, JM, DC), pp. 32–41.
LCTES-2011-JangKLKYKKR #architecture #clustering #configuration management: An instruction-scheduling-aware data partitioning technique for coarse-grained reconfigurable architectures (CJ, JK, JL, HSK, DY, SK, HK, SR), pp. 151–160.
DAC-2010-LiangM #reuse #using: Instruction cache locking using temporal reuse profile (YL, TM), pp. 344–349.
DATE-2010-BorodinJ #detection #fault: Instruction precomputation with memoization for fault detection (DB, BHHJ), pp. 1665–1668.
DATE-2010-KoenigBSSABH #architecture #configuration management #multi #named #novel: KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array architecture (RK, LB, TS, MS, WA, JB, JH), pp. 819–824.
ITiCSE-2010-KarakostasDRA #multi #programming: e-Lectures to support blended instruction in multimedia programming course (AK, SND, VR, MA), pp. 189–193.
ITiCSE-2010-RagonisH #design #paradigm #programming: Linking different programming paradigms: thoughts about instructional design (NR, BH), p. 310.
ITiCSE-2010-WangDWS #database: Undergraduate database instruction with MeTube (JZW, TAD, JW, PKS), pp. 279–283.
PLDI-2010-YangH #automation #operating system #type safety #verification: Safe to the last instruction: automated verification of a type-safe operating system (JY, CH), pp. 99–110.
ILC-2010-YuasaY #low level #using #validation: Validating low-level instructions for fixnums using BDDs (SY, MY), pp. 11–20.
SEKE-2010-SilvaS #classification #data mining #knowledge base #mining #modelling #relational #testing: Modeling and Testing a Knowledge Base for Instructing Users to Choose the Classification Task in Relational Data Mining (LMdS, AEAdS), pp. 608–613.
POPL-2010-DiasR #automation #declarative #generative #using: Automatically generating instruction selectors using declarative machine descriptions (JD, NR), pp. 403–416.
CGO-2010-KochBF #code generation: Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions (TJKEvK, IB, BF), pp. 180–189.
HPCA-2010-RomanescuLSB #protocol: UNified Instruction/Translation/Data (UNITD) coherence: One protocol to rule them all (BFR, ARL, DJS, AB), pp. 1–12.
LCTES-2010-LiXLZ #analysis #approximate #architecture #memory management: Analysis and approximation for bank selection instruction minimization on partitioned memory architecture (ML, CJX, TL, YZ), pp. 1–8.
DAC-2009-BonnyH #named #performance: LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors (TB, JH), pp. 903–906.
DAC-2009-GeMW #configuration management #memory management #pipes and filters: A DVS-based pipelined reconfigurable instruction memory (ZG, TM, WFW), pp. 897–902.
DAC-2009-KluterBIC #automation #set: Way Stealing: cache-assisted automatic instruction set extensions (TK, PB, PI, EC), pp. 31–36.
DAC-2009-LaiYKH #performance #realtime: A trace-capable instruction cache for cost efficient real-time program trace compression in SoC (CHL, FCY, CFK, IJH), pp. 136–141.
DATE-2009-GaluzziTMB #algorithm #automation: Algorithms for the automatic extension of an instruction-set (CG, DT, RM, KB), pp. 548–553.
DATE-2009-GuanLF #design #scalability #set: Design of an application-specific instruction set processor for high-throughput and scalable FFT (XG, HL, YF), pp. 1302–1307.
DATE-2009-HuynhM #configuration management #embedded #realtime #runtime: Runtime reconfiguration of custom instructions for real-time embedded systems (HPH, TM), pp. 1536–1541.
DATE-2009-LiFNBPC #architecture #co-evolution #design #detection #ml #parallel #set: Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors (ML, RF, DN, BB, LVdP, FC), pp. 1608–1613.
DATE-2009-PatelPR #architecture #framework #named #security: CUFFS: An instruction count based architectural framework for security of MPSoCs (KP, SP, RGR), pp. 779–784.
ITiCSE-2009-BuendiaCB #approach #learning: An instructional approach to drive computer science courses through virtual learning environments (FB, JCC, JVB), pp. 6–10.
ITiCSE-2009-ChandrasekarTP #effectiveness #tablet: WriteOn1.0: a tablet PC-based tool for effective classroom instruction (SC, JGT, JCP), pp. 323–327.
CHI-2009-SpelmezanJHB #physics #process: Tactile motion instructions for physical activities (DS, MJ, AH, JOB), pp. 2243–2252.
HCI-NIMT-2009-Whitman #diagrams #effectiveness: The Effectiveness of Interactivity in Computer-Based Instructional Diagrams (LW), pp. 899–908.
HCI-VAD-2009-MitsuishiKHG #concept #distance #interactive #realtime: The Concept of IMPRESSION: An Interactive Instruction System and Its Practice for Real-Time Distance Lessons between U.S. and Japan (TM, FK, YH, KG), pp. 176–185.
CC-2009-FarooqJ #architecture #data flow #scheduling: Loop-Aware Instruction Scheduling with Dynamic Contention Tracking for Tiled Dataflow Architectures (MUF, LKJ), pp. 190–203.
CGO-2009-CollinB #embedded #taxonomy: Two-Level Dictionary Code Compression: A New Scheme to Improve Instruction Code Density of Embedded Applications (MC, MB), pp. 231–242.
LCTES-2009-HinesPGWT #behaviour #lookahead: Guaranteeing instruction fetch behavior with a lookahead instruction fetch engine (LIFE) (SRH, YP, PG, DBW, GST), pp. 119–128.
DAC-2008-BauerSH #embedded #runtime #set: Run-time instruction set selection in a transmutable embedded processor (LB, MS, JH), pp. 56–61.
DAC-2008-LiBNPC #approach #how #implementation #power management #set: How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach (ML, BB, DN, LVdP, FC), pp. 345–346.
DAC-2008-ParkM #analysis #debugging #locality #named: IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors (SBP, SM), pp. 373–378.
DAC-2008-TarjanBS #named: Federation: repurposing scalar cores for out-of-order instruction issue (DT, MB, KS), pp. 772–775.
DATE-2008-BauerSKH #embedded #runtime #set: Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set (LB, MS, SK, JH), pp. 752–757.
DATE-2008-BonnyH #embedded #encoding: Instruction Re-encoding Facilitating Dense Embedded Code (TB, JH), pp. 770–775.
DATE-2008-JonesBBCO #compilation #energy: Instruction Cache Energy Saving Through Compiler Way-Placement (TMJ, SB, BDB, JC, MFPO), pp. 1196–1201.
DATE-2008-KleanthousS #detection #named: CATCH: A Mechanism for Dynamically Detecting Cache-Content-Duplication and its Application to Instruction Caches (MK, YS), pp. 1426–1431.
DATE-2008-LiNBPC #architecture #multi: Generic Multi-Phase Software-Pipelined Partial-FFT on Instruction-Level-Parallel Architectures and SDR Baseband Applications (ML, DN, BB, LVdP, FC), pp. 598–603.
DATE-2008-LinF #parallel #performance #source code: Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency (HL, YF), pp. 758–763.
DATE-2008-VogtW #configuration management #set: A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment (TV, NW), pp. 38–43.
DATE-2008-WuCSC #architecture #multi #set: Instruction Set Extension Exploration in Multiple-Issue Architecture (IWW, ZYC, JJJS, CPC), pp. 764–769.
ITiCSE-2008-Bower #learning #online: The “instructed-teacher”: a computer science online learning pedagogical pattern (MB), pp. 189–193.
ITiCSE-2008-Hollingsworth #approach #education #query: Teaching query writing: an informed instruction approach (JEH), p. 351.
QAPL-2008-LambertP #bytecode #framework #independence #java #virtual machine: Platform Independent Timing of Java Virtual Machine Bytecode Instructions (JML, JFP), pp. 97–113.
POPL-2008-TristanL #case study #optimisation #scheduling #validation #verification: Formal verification of translation validators: a case study on instruction scheduling optimizations (JBT, XL), pp. 17–27.
SAC-2008-BallabrigaCS #analysis #approach: An improved approach for set-associative instruction cache partial analysis (CB, HC, PS), pp. 360–367.
SAC-2008-GiorgiB #performance: Filtering drowsy instruction cache to achieve better efficiency (RG, PB), pp. 1554–1555.
SAC-2008-SykoraAS #embedded #pipes and filters: Dynamic configuration of application-specific implicit instructions for embedded pipelined processors (MS, GA, CS), pp. 1509–1516.
ASPLOS-2008-OttoniA #communication #concurrent #multi #optimisation #scheduling #thread: Communication optimizations for global multi-threaded instruction scheduling (GO, DIA), pp. 222–232.
CC-2008-LimR #bytecode #generative: A System for Generating Static Analyzers for Machine Instructions (JL, TWR), pp. 36–52.
CGO-2008-KoesG #graph: Near-optimal instruction selection on dags (DRK, SCG), pp. 45–54.
HPCA-2008-KumarA #trade-off #validation: Speculative instruction validation for performance-reliability trade-off (SK, AA), pp. 405–414.
HPCA-2008-WellsS: Serializing instructions in system-intensive workloads: Amdahl’s Law strikes again (PMW, GSS), pp. 264–275.
LCTES-2008-EbnerBSKWK #using: Generalized instruction selection using SSA-graphs (DE, FB, BS, AK, PW, AK), pp. 31–40.
DAC-2007-BauerSKH #framework #named #set: RISPP: Rotating Instruction Set Processing Platform (LB, MS, SK, JH), pp. 791–796.
DAC-2007-BonnyH #performance: Instruction Splitting for Efficient Code Compression (TB, JH), pp. 646–651.
DAC-2007-MorganT #encoding #energy #reduction: ASIP Instruction Encoding for Energy and Area Reduction (PM, RT), pp. 797–800.
DATE-2007-AtasuDMLOD #constraints #optimisation: Optimizing instruction-set extensible processors under data bandwidth constraints (KA, RGD, OM, WL, CCÖ, GD), pp. 588–593.
DATE-2007-BonziniP #automation #polynomial #set: Polynomial-time subgraph enumeration for automated instruction set extension (PB, LP), pp. 1331–1336.
DATE-2007-FeiS #architecture #monitoring #set: Microarchitectural support for program code integrity monitoring in application-specific instruction set processors (YF, ZJS), pp. 815–820.
DATE-2007-GeWL #configuration management #embedded #memory management #named #power management: DRIM: a low power dynamically reconfigurable instruction memory hierarchy for embedded systems (ZG, WFW, HBL), pp. 1343–1348.
DATE-2007-HuynhM #embedded #realtime: Instruction-set customization for real-time embedded systems (HPH, TM), pp. 1472–1477.
DATE-2007-JanapsatyaIPH #agile #simulation: Instruction trace compression for rapid instruction cache simulation (AJ, AI, SP, JH), pp. 803–808.
DATE-2007-KhanA #architecture #configuration management #implementation #pipes and filters #programmable #realtime: Pipelined implementation of a real time programmable encoder for low density parity check code on a reconfigurable instruction cell architecture (ZK, TA), pp. 349–354.
DATE-2007-NooriMMIG #adaptation #generative #interactive #multi: Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor (HN, FM, KM, KI, MG), pp. 325–330.
ITiCSE-2007-Dickinson07b #navigation: Is the shortcut the quickest way to go?: translating instructions for keyboard navigation and other stories (AD), p. 358.
ITiCSE-2007-MullerGH #composition #problem: Pattern-oriented instruction and its influence on problem decomposition and solution construction (OM, DG, BH), pp. 151–155.
ITiCSE-2007-PapadopoulosDS #education #project management #web: Case-based instruction on the web for teaching software project management (PMP, SND, IS), pp. 136–140.
HCI-AS-2007-SunH #case study: A Study of Learners’ Perceptions of the Interactivity of Web-Based Instruction (JnS, YcH), pp. 351–360.
HCI-IPT-2007-AsaiK #comparative: Comparative Characteristics of a Head-Up Display for Computer-Assisted Instruction (KA, HK), pp. 531–540.
HCI-MIE-2007-YecanSBC #behaviour #multimodal: Tracing Users’ Behaviors in a Multimodal Instructional Material: An Eye-Tracking Study (EY, ES, BB, KÇ), pp. 755–762.
HIMI-IIE-2007-LiuK: Skill Transfer from Expert to Novice — Instruction Manuals Made by Means of Groupware (CYL, YK), pp. 423–429.
OCSC-2007-Huang #case study #library #social: Integrating Digital Library Resources in Elementary School Classrooms — A Case Study of Social Study Instruction (KHH), pp. 372–374.
LCTES-2007-BennettMFT #automation #embedded #set #text-to-text: Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems (RVB, ACM, BF, NPT), pp. 83–92.
LCTES-2007-HinesTW #using: Addressing instruction fetch bottlenecks by using an instruction register file (SRH, GST, DBW), pp. 165–174.
LCTES-2007-YanZ #analysis: WCET analysis of instruction caches with prefetching (JY, WZ), pp. 175–184.
ICLP-2007-Zhou #prolog: A Register-Free Abstract Prolog Machine with Jumbo Instructions (NFZ), pp. 455–457.
DAC-2006-JayaseelanLM: Exploiting forwarding to improve data bandwidth of instruction-set extensions (RJ, HL, TM), pp. 43–48.
DAC-2006-StojanovicBDW #effectiveness #implementation #queue: A cost-effective implementation of an ECC-protected instruction queue for out-of-order microprocessors (VS, RIB, JD, RW), pp. 705–708.
DATE-2006-DErricoQ #approach: Constructing portable compiled instruction-set simulators: an ADL-driven approach (JD, WQ), pp. 112–117.
DATE-2006-GrossschadlIPTV #algorithm #case study #design #encryption #set: Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography (JG, PI, LP, ST, AKV), pp. 218–223.
DATE-2006-LeupersKKP #configuration management #design #embedded #set #synthesis: A design flow for configurable embedded processors based on optimized instruction set extension synthesis (RL, KK, SK, MP), pp. 581–586.
DATE-2006-YiNMKAL #configuration management #scheduling: System-level scheduling on instruction cell based reconfigurable systems (YY, IN, MM, SK, TA, IL), pp. 381–386.
DATE-DF-2006-KappenN #implementation: Application specific instruction processor based implementation of a GNSS receiver on an FPGA (GK, TGN), pp. 58–63.
CSEET-2006-BasiliB #education #re-engineering: Software Engineering Instruction and Education Theory: A Dialogue (PAB, VRB), p. 6.
CSEET-2006-WallaceWB #analysis #problem: Instruction in Problem Structuring and Analysis Through Problem Frames (CW, XW, VB), pp. 185–186.
PLDI-2006-BridgesVOA #automation: Automatic instruction scheduler retargeting by reverse-engineering (MJB, NV, GO, DIA), pp. 228–238.
PLDI-2006-ErtlCG #automaton #flexibility #on-demand #performance: Fast and flexible instruction selection with on-demand tree-parsing automata (MAE, KC, DG), pp. 52–60.
CSCW-2006-KoschmannLGF #problem: The mystery of the missing referent: objects, procedures, and the problem of the instruction follower (TK, CL, CG, PJF), pp. 373–382.
ICEIS-HCI-2006-Patokorpi #learning: Constructivist Instructional Principles, Learner Psychology and Technological Enablers of Learning (EP), pp. 103–109.
QAPL-2005-BartheRW06 #branch #transaction: Preventing Timing Leaks Through Transactional Branching Instructions (GB, TR, MW), pp. 33–55.
QAPL-2005-BinderH06 #bytecode #cpu #metric #using: Using Bytecode Instruction Counting as Portable CPU Consumption Metric (WB, JH), pp. 57–77.
QAPL-2006-BinderH06a #bytecode #profiling #using #virtual machine: Exact and Portable Profiling for the JVM Using Bytecode Instruction Counting (WB, JH), pp. 45–64.
ICSE-2006-DamianHA #assessment #design #development #education #framework: Instructional design and assessment strategies for teaching global software development: a framework (DED, AH, BAA), pp. 685–690.
ASPLOS-2006-KawahitoKMIN #framework #recognition: A new idiom recognition framework for exploiting hardware-assist instructions (MK, HK, TM, HI, TN), pp. 382–393.
ASPLOS-2006-MercaldiSPPSOE #architecture #data flow #scheduling: Instruction scheduling for a tiled dataflow architecture (MM, SS, AP, AP, AS, MO, SJE), pp. 141–150.
ASPLOS-2006-MillerA #embedded: Software-based instruction caching for embedded processors (JEM, AA), pp. 293–302.
CGO-2006-LiZXH #optimisation: Optimizing Dynamic Binary Translation for SIMD Instructions (JL, QZ, SX, BH), pp. 269–280.
HPCA-2006-PericasCGJV: A decoupled KILO-instruction processor (MP, AC, RG, DAJ, MV), pp. 53–64.
HPCA-2006-SharkeyP #performance #smt: Efficient instruction schedulers for SMT processors (JJS, DVP), pp. 288–298.
LCTES-2006-ParkSDNPE #reduction #scheduling: Bypass aware instruction scheduling for register file power reduction (SP, AS, NDD, AN, YP, EE), pp. 173–181.
DATE-2005-BiswasBDPI #generative #named #set: ISEGEN: Generation of High-Quality Instruction Set Extensions by Iterative Improvement (PB, SB, NDD, LP, PI), pp. 1246–1251.
DATE-2005-CengHLAMB #c #compilation #modelling #semantics: C Compiler Retargeting Based on Instruction Semantics Models (JC, MH, RL, GA, HM, GB), pp. 1150–1155.
DATE-2005-HuLDKVI #detection #fault: Compiler-Directed Instruction Duplication for Soft Error Detection (JSH, FL, VD, MTK, NV, MJI), pp. 1056–1057.
DATE-2005-PanainteBV #hardware #scheduling: Instruction Scheduling for Dynamic Hardware Configurations (EMP, KB, SV), pp. 100–105.
SCAM-2005-BermudoKH #assembly #control flow #graph #re-engineering #source code: Control Flow Graph Reconstruction for Assembly Language Programs with Delayed Instructions (NB, AK, RNH), pp. 107–118.
CC-2005-JiangMHLZZZ #multi #performance #using: Boosting the Performance of Multimedia Applications Using SIMD Instructions (WJ, CM, BH, JL, JZ, BZ, CZ), pp. 59–75.
CGO-2005-RavindranNDMSMB #compilation #power management: Compiler Managed Dynamic Instruction Placement in a Low-Power Code Cache (RAR, PDN, GSD, EDM, RMS, SAM, RBB), pp. 179–190.
HPCA-2005-JaleelJ #memory management #using: Using Virtual Load/Store Queues (VLSQs) to Reduce the Negative Effects of Reordered Memory Instructions (AJ, BLJ), pp. 191–200.
HPCA-2005-SpracklenCA #effectiveness #multi: Effective Instruction Prefetching in Chip Multiprocessors for Modern Commercial Applications (LS, YC, SGA), pp. 225–236.
LCTES-2005-BriskMNS #taxonomy: A dictionary construction technique for code compression systems with echo instructions (PB, JM, AN, MS), pp. 105–114.
DAC-2004-BiswasCAPID #memory management #set: Introduction of local memory elements in instruction set extensions (PB, VC, KA, LP, PI, ND), pp. 729–734.
DAC-2004-BriskKS #configuration management #design #set #synthesis: Area-efficient instruction set synthesis for reconfigurable system-on-chip designs (PB, AK, MS), pp. 395–400.
DAC-2004-ChengTM #embedded #named #synthesis: FITS: framework-based instruction-set tuning synthesis for embedded application specific processors (ACC, GST, TNM), pp. 920–923.
DAC-2004-YuM #embedded: Characterizing embedded applications for instruction-set extensible processors (PY, TM), pp. 723–728.
DATE-v1-2004-HuVKKI #reduction #reuse #scheduling: Scheduling Reusable Instructions for Power Reduction (JSH, NV, SK, MTK, MJI), pp. 148–155.
DATE-v1-2004-KuoHW #composition #design #power management: Decomposition of Instruction Decoder for Low Power Design (WAK, TH, ACHW), pp. 664–665.
DATE-v1-2004-WangH #clustering #memory management #multi #power management #scheduling: Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks (ZW, XSH), pp. 312–317.
DATE-v1-2004-WongT #configuration management #encoding #power management: Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus (SKW, CYT), pp. 130–135.
DATE-v2-2004-AragonNVB #design #embedded #energy: Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors (JLA, DN, AVV, AMB), pp. 1374–1375.
DocEng-2004-Francisco-RevillaS #adaptation #hypermedia: Instructional information in adaptive spatial hypertext (LFR, FMSI), pp. 124–133.
SIGMOD-2004-ZhouR #database #performance: Buffering Database Operations for Enhanced Instruction Cache Performance (JZ, KAR), pp. 191–202.
ITiCSE-2004-Ginat #design: Embedding instructive assertions in program design (DG), pp. 62–66.
ITiCSE-2004-MullerHA #problem: (An almost) pedagogical pattern for pattern-based problem-solving instruction (OM, BH, HA), pp. 102–106.
ICEIS-v5-2004-ChangT #design: The Meeting of Gestalt and Cognitive Load Theories in Instructional Screen Design (DC, JT), pp. 53–62.
CC-2004-JohnsonM #memory management #multi #using: Using Multiple Memory Access Instructions for Reducing Code Size (NJ, AM), pp. 265–280.
CGO-2004-HuS #using: Using Dynamic Binary Translation to Fuse Dependent Instructions (SH, JES), pp. 213–226.
HPCA-2004-AamodtCHWS #hardware: Hardware Support for Prescient Instruction Prefetch (TMA, PC, PH, HW, JPS), pp. 84–95.
HPCA-2004-HuVI #scheduling: Exploring Wakeup-Free Instruction Scheduling (JSH, NV, MJI), pp. 232–243.
LCTES-2004-KastensLST #feedback: Feedback driven instruction-set extension (UK, DKL, AS, MT), pp. 126–135.
LCTES-2004-PatilSM #composition #simulation: Compositional static instruction cache simulation (KP, KS, FM), pp. 136–145.
DAC-2003-AtasuPI #architecture #automation #constraints: Automatic application-specific instruction-set extensions under microarchitectural constraints (KA, LP, PI), pp. 256–261.
DAC-2003-MoreshetB #design #power management #queue: Power-aware issue queue design for speculative instructions (TM, RIB), pp. 634–637.
DAC-2003-NohlGBALSM #architecture #encoding #modelling #synthesis #using: Instruction encoding synthesis for architecture exploration using hierarchical processor models (AN, VG, GB, AH, RL, OS, HM), pp. 262–267.
DAC-2003-ReshadiMD #flexibility #performance #set #simulation: Instruction set compiled simulation: a technique for fast and flexible instruction set simulation (MR, PM, NDD), pp. 758–763.
DATE-2003-CheungHP #agile #case study: Rapid Configuration and Instruction Selection for an ASIP: A Case Study (NC, JH, SP), pp. 10802–10809.
DATE-2003-PetrovO #memory management #performance: Power Efficiency through Application-Specific Instruction Memory Transformations (PP, AO), pp. 10030–10035.
DATE-2003-RebaudengoRV #analysis #fault #pipes and filters: An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor (MR, MSR, MV), pp. 10602–10607.
DATE-2003-SchnerrHR #agile #prototype #set: Instruction Set Emulation for Rapid Prototyping of SoCs (JS, GH, WR), pp. 10562–10569.
DATE-2003-SurendraBN #network #reuse: Enhancing Speedup in Network Processing Applications by Exploiting Instruction Reuse with Flow Aggregation (GS, SB, SKN), pp. 10784–10789.
ITiCSE-2003-RedmondWP: Equilibriating instructional media for cognitive styles (JAR, CW, AP), pp. 55–59.
ICEIS-v2-2003-DoderoDA #collaboration #design #evaluation #protocol: Evaluation of an Agent-Mediated Collaborative Production Protocol in an Instructional Design Scenario (JMD, PD, IA), pp. 52–57.
SAC-2003-Valverde-AlbacetePCDNM #design #named: InterMediActor: an Environment for Instructional Content Design Based on Competences (FJVA, RPJ, JCS, PDP, ANV, HYMB), pp. 575–579.
HPCA-2003-MutluSWP #execution #scalability: Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors (OM, JS, CW, YNP), pp. 129–140.
LCTES-2003-KimVKI #adaptation #architecture #optimisation #parallel: Adapting instruction level parallelism for optimizing leakage in VLIW architectures (HSK, NV, MTK, MJI), pp. 275–283.
LCTES-2003-Krishnaswamy #performance #using: Enhancing the performance of 16-bit code using augmenting instructions (AK, RG), pp. 254–264.
DAC-2002-BonaSSZSZ #clustering #embedded #energy #estimation #optimisation: Energy estimation and optimization of embedded VLIW processors based on instruction clustering (AB, MS, DS, VZ, CS, RZ), pp. 886–891.
DAC-2002-NohlBSLMH #architecture #flexibility #performance #simulation: A universal technique for fast and flexible instruction-set architecture simulation (AN, GB, OS, RL, HM, AH), pp. 22–27.
DATE-2002-BonaSSZSZ #embedded #estimation #optimisation: An Instruction-Level Methodology for Power Estimation and Optimization of Embedded VLIW Cores (AB, MS, DS, VZ, CS, RZ), p. 1128.
DATE-2002-PozziVI #automation #embedded #identification: Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors (LP, MV, PI), p. 1138.
DATE-2002-ZhaoMB #compilation #design #modelling #set #using: Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models (QZ, BM, TB), pp. 1021–1026.
SIGMOD-2002-ZhouR #database #implementation #using: Implementing database operations using SIMD instructions (JZ, KAR), pp. 145–156.
ITiCSE-2002-Scott #named #set: MISC: the minimal instruction set computer (KS), p. 223.
PASTE-2002-AkgulM #debugging #execution: Instruction-level reverse execution for debugging (TA, VJM), pp. 18–25.
SIGIR-2002-SormunenHKPS #information retrieval #performance #query #research: Query performance analyser: a web-based tool for IR research and instruction (ES, SH, PK, PP, BS), p. 450.
ECOOP-2002-HovemeyerPS #java: Atomic Instructions in Java (DH, WP, JS), pp. 133–154.
SAC-2002-NunnD #assembly #automation #component: Automated assembly of software components based on XML-coded instructions (IN, DD), pp. 937–942.
ASPLOS-2002-ButtsS #detection: Dynamic dead-instruction detection and elimination (JAB, GSS), pp. 199–210.
LCTES-SCOPES-2002-KrishnaswamyG: Profile guided selection of ARM and thumb instructions (AK, RG), pp. 56–64.
LCTES-SCOPES-2002-LorenzWD #compilation #energy: Energy aware compilation for DSPs with SIMD instructions (ML, LW, TD), pp. 94–101.
RTA-2002-BravenboerV: Rewriting Strategies for Instruction Selection (MB, EV), pp. 237–251.
DAC-2001-LaiC #testing: Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip (WCL, KTC), pp. 59–64.
DAC-2001-WangKMR #hardware #set: Hardware/Software Instruction Set Configurability for System-on-Chip Processors (AW, EK, DEM, CR), pp. 184–188.
DATE-2001-ShinKC #optimisation: An operation rearrangement technique for power optimization in VLIM instruction fetch (DS, JK, NC), p. 809.
ITiCSE-2001-Huizinga #identification #online #programming #topic: Identifying topics for instructional improvement through on-line tracking of programming assignments (DMH), pp. 129–132.
ITiCSE-2001-LanariR #authoring #education #named: e-IMC: an authoring tool for humanistic teachers aimed to develop and distribute customized instructional courseware (DL, SR), p. 183.
ITiCSE-2001-ShiSC #component: Smart instructional component based course content organization and delivery (HS, YS, SSC), p. 186.
PPDP-2001-NassenCS #prolog #virtual machine: Instruction Merging and Specialization in the SICStus Prolog Virtual Machine (HN, MC, KFS), pp. 49–60.
CC-2001-Gregg #scheduling: Comparing Tail Duplication with Compensation Code in Single Path Global Instruction Scheduling (DG), pp. 200–212.
HPCA-2001-MichaudS #data flow #scalability: Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors (PM, AS), pp. 27–36.
HPCA-2001-SrinivasanDTCP #branch: Branch History Guided Instruction Prefetching (VS, ESD, GST, MJC, TRP), pp. 291–300.
HPCA-2001-TuneLTC #predict: Dynamic Prediction of Critical Path Instructions (ET, DL, DMT, BC), pp. 185–195.
LCTES-OM-2001-KastnerW #scheduling: ILP-based Instruction Scheduling for IA-64 (DK, SW), pp. 145–154.
LCTES-OM-2001-LeeEMC #embedded #energy: An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors (SL, AE, SLM, NC), pp. 1–10.
IJCAR-2001-FormisanoOT #equation: Instructing Equational Set-Reasoning with Otter (AF, EGO, MT), pp. 152–167.
DAC-2000-BrandoleseFSS #energy #estimation: An instruction-level functionally-based energy estimation model for 32-bits microprocessors (CB, WF, FS, DS), pp. 346–351.
DATE-2000-Leupers: Code Selection for Media Processors with SIMD Instructions (RL), pp. 4–8.
HT-2000-ThomsonGC #generative #hypermedia: Generating instructional hypermedia with APHID (JRT, JEG, JC), pp. 248–249.
ITiCSE-2000-OuCLL #learning #web: Instructional instruments for Web group learning systems: the grouping, intervention, and strategy (KLO, GDC, CCL, BJL), pp. 69–72.
ITiCSE-2000-Weber-Wulff #programming: Combating the code warrior: a different sort of programming instruction (DWW), pp. 85–88.
TACAS-2000-AronsP #comparison #execution #verification: A Comparison of Two Verification Methods for Speculative Instruction Execution (TA, AP), pp. 487–502.
PLDI-2000-LarsenA #parallel #set: Exploiting superword level parallelism with multimedia instruction sets (SL, SPA), pp. 145–156.
PLDI-2000-WilkenLH #integer #programming #scheduling #using: Optimal instruction scheduling using integer programming (KDW, JL, MH), pp. 121–133.
CHI-2000-CorbettT #difference #learning: Instructional interventions in computer-based tutoring: differential impact on learning time and accuracy (ATC, HJT), pp. 97–104.
CADE-2000-MichaelA #bytecode #higher-order #logic #semantics #syntax: Machine Instruction Syntax and Semantics in Higher Order Logic (NGM, AWA), pp. 7–24.
DAC-1999-Fisher #embedded: Customized Instruction-Sets for Embedded Processors (JAF), pp. 253–257.
DATE-1999-Leupers #code generation #embedded: Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors (RL), p. 105–?.
ITiCSE-1999-Impagliazzo #architecture #education #scalability #word: Teaching very large instruction word architectures (JI), p. 208.
ITiCSE-1999-KurasGZ #education: Changing IS curriculum and methods of instruction (MK, MG, AZ), pp. 36–39.
ITiCSE-1999-ScherzP #learning: An organizer for project-based learning and instruction in computer science (ZS, SP), pp. 88–90.
ITiCSE-1999-Taylor99a #education #learning: Math link: linking curriculum, instructional strategies, and technology to enhance teaching and learning (HGT), p. 201.
ITiCSE-1999-Trichina #topic: Didactic instructional tool for topics in computer science (ET), pp. 95–98.
PLDI-1999-StichnothLC #compilation #garbage collection #java: Support for Garbage Collection at Every Instruction in a Java Compiler (JMS, GYL, MC), pp. 118–127.
HCI-CCAD-1999-Murphy #online: On-line instruction in assistive technology (HJM), pp. 848–852.
HPCA-1999-JacobsonS #preprocessor: Instruction Pre-Processing in Trace Processors (QJ, JES), pp. 125–129.
HPCA-1999-KaxirasG #performance #predict #using: Improving CC-NUMA Performance Using Instruction-Based Prediction (SK, JRG), pp. 161–170.
HPCA-1999-WallaceTC #multi: Instruction Recycling on a Multiple-Path Processor (SW, DMT, BC), pp. 44–53.
DAC-1998-HanonoD #code generation #resource management #scheduling: Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator (SH, SD), pp. 510–515.
DATE-1998-TomiyamaIIY #design #reduction #scheduling: Instruction Scheduling for Power Reduction in Processor-Based System Design (HT, TI, AI, HY), pp. 855–860.
ITiCSE-1998-AbernethyGT #case study #experience: Inquiry-based computer science instruction: some initial experiences (KA, PG, KT), pp. 14–17.
ITiCSE-1998-Astrachan #education: Concrete teaching: hooks and props as instructional technology (OLA), pp. 21–24.
ITiCSE-1998-Cooper #design #internet: Designing Internet instructional environments (poster) (PAC), p. 275.
ITiCSE-1998-DavidovicT #learning: Open learning environment and instruction system (OLEIS) (AD, ET), pp. 69–73.
ITiCSE-1998-Johansson #approach #programming #student: Programming by example (poster): an instructional approach allowing introductory students to quickly grasp the power and excitement of programming (PGJ), p. 284.
ITiCSE-1998-Kotze #hypermedia #why: Why the hypermedia model is inadequate for computer-based instruction (PK), pp. 148–152.
WRLA-1998-Jouannaud #calculus #equation #induction #logic: Membership equational logic, calculus of inductive instructions, and rewrite logic (JPJ), pp. 388–393.
IWPC-1998-CifuentesS #bytecode #semantics #specification: Specifying the Semantics of Machine Instructions (CC, SS), pp. 126–133.
ICML-1998-SalustowiczS #evolution #source code: Evolving Structured Programs with Hierarchical Instructions and Skip Nodes (RS, JS), pp. 488–496.
ASPLOS-1998-LeeBFSBSA #parallel #scheduling: Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine (WL, RB, MF, DS, JB, VS, SPA), pp. 46–57.
ASPLOS-1998-SodaniS #analysis #empirical: An Empirical Analysis of Instruction Repetition (AS, GSS), pp. 35–45.
CC-1998-Gupta #framework #scheduling: A Code Motion Framework for Global Instruction Scheduling (RG), pp. 219–233.
HPCA-1998-KalamatianosK #order #performance: Temporal-Based Procedure Reordering for Improved Instruction Cache Performance (JK, DRK), pp. 244–253.
LCTES-1998-CooperS #scheduling: Non-local Instruction Scheduling with Limited Code Growth (KDC, PJS), pp. 193–207.
LCTES-1998-LundqvistS #analysis #simulation #using: Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques (TL, PS), pp. 1–15.
DAC-1997-HadjiyiannisHD #named #set: ISDL: An Instruction Set Description Language for Retargetability (GH, SH, SD), pp. 299–302.
EDTC-1997-LiemPJ #design #embedded #named: ReCode: the design and re-design of the instruction codes for embedded instruction-set processors (CL, PGP, AAJ), p. 612.
ICDAR-1997-NakagawaHYSHA #database #online #sequence: On-line Handwritten Character Pattern Database Sampled in a Sequence of Sentences without any Writing Instructions (MN, TH, YY, SiS, LH, KA), pp. 376–381.
ITiCSE-1997-BeheshtiW: Instructional software for closed laboratories in CS1 (MB, BW), pp. 40–41.
ITiCSE-1997-Cizmar #experience #research #student: CS student research experience applied to developing instructional technology (DC), pp. 120–126.
ITiCSE-1997-Naps97a #interactive #using #visualisation: Using the WWW as the delivery mechanism for interactive, visualization-based instructional modules (panel) (TLN), p. 143.
ITiCSE-WGR-1997-NapsBJMPPT #interactive #using #visualisation: Using the WWW as the delivery mechanism for interactive, visualization-based instructional modules (report of the ITiCSE 1997 working group on visualization) (TLN, JB, RJP, MFM, MPM, VKP, JT), pp. 13–26.
HCI-SEC-1997-AsiuM #design #reasoning #theory and practice: The Role of Case-Based Reasoning in Instructional Design: Theory and Practice (BA, MDM), pp. 153–156.
HCI-SEC-1997-KitajimaP #human-computer #interactive: Mapping Instructions onto Actions: A Comprehension-Based Model of Display-Based Human-Computer Interaction (MK, PGP), pp. 83–86.
HCI-SEC-1997-KuzuokaN #using: Assisting Remote Instruction Using Copied Reality (HK, TN), pp. 957–960.
ICSE-1997-FernandezR #automation #specification: Automatic Checking of Instruction Specifications (MFF, NR), pp. 326–336.
HPCA-1997-PaiRA #parallel #performance #simulation: The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology (VSP, PR, SVA), pp. 72–83.
DAC-1996-LiemPJ #architecture #compilation: Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures (CL, PGP, AAJ), pp. 597–600.
ITiCSE-1996-MalyWOAGYSTP #case study #experience #interactive: Interactive remote instruction: initial experiences (KM, JCW, CMO, HMAW, AG, AY, ES, RT, AP), pp. 153–155.
PLDI-1996-Ramsey #bytecode: Relocating Machine Instructions by Currying (NR), pp. 226–236.
WIA-1996-JohnsonW #set: Instruction Computation in Subset Construction (JHJ, DW), pp. 64–71.
CHI-1996-PaneCJ: Assessing Dynamics in Computer-Based Instruction (JFP, ATC, BEJ), pp. 197–204.
ICPR-1996-BabaguchiDK #comprehension #generative #image #sketching: Generation of sketch map image and its instructions to support the understanding of geographical information (NB, SD, TK), pp. 274–278.
DAC-1995-TimmerSMJ #code generation #modelling #scheduling: Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores (AHT, MTJS, JLvM, JAGJ), pp. 593–598.
ICDAR-v1-1995-KaneharaSH #flexibility #image #retrieval #using #visual notation: A flexible image retrieval using explicit visual instruction (FK, SS, TH), pp. 175–178.
PLDI-1995-LoE #compilation #optimisation #parallel #scheduling: Improving Balanced Scheduling with Compiler Optimizations that Increase Instruction-Level Parallelism (JLL, SJE), pp. 151–162.
CHI-1995-Harrison #comparison #online #user interface #visual notation: A Comparison of Still, Animated, or Nonillustrated On-Line Help with Written or Spoken Instructions in a Graphical User Interface (SMH), pp. 82–89.
SAC-1995-AndrusN #named #simulation: SCAD: a computer generated simulation for audit instruction (JMA, MSN), pp. 14–16.
HPCA-1995-TorrellasXD #operating system #optimisation #performance: Optimizing Instruction Cache Performance for Operating System Intensive Workloads (JT, CX, RLD), pp. 360–369.
HPCA-1995-Weiss #implementation #multi #queue: Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors (SW), pp. 14–21.
LCT-RTS-1995-HuangL #concurrent #execution #predict #worst-case: Predicting the Worst-Case Execution Time of the Concurrent Execution of Instructions and Cycle-Stealing DMA I/O Operations (TYH, JWSL), pp. 1–6.
DAC-1994-HuangD #pipes and filters #set #synthesis: Synthesis of Instruction Sets for Pipelined Microprocessors (IJH, AMD), pp. 5–11.
EDAC-1994-LiemMP #code generation: Instruction-Set Matching and Selection for DSP and ASIP Code Generation (CL, TCM, PGP), pp. 31–37.
KR-1994-Eugenio #natural language #representation: Action Representation for Interpreting Purpose Clauses in Natural Language Instructions (BDE), pp. 158–169.
CC-1994-ErtlK #exception #execution: Delayed Exceptions — Speculative Execution of Trapping Instructions (MAE, AK), pp. 158–171.
CC-1994-MahadevanR #framework #scheduling: Instruction Schedulimg over Regions: A Framework for Scheduling Across Basic Blocks (UM, SR), pp. 419–434.
CC-1994-MendlsonPS #optimisation: Compile Time Instruction Cache Optimizations (AM, SSP, RS), pp. 404–418.
DAC-1993-CloutierT #pipes and filters #set #synthesis: Synthesis of Pipelined Instruction Set Processors (RJC, DET), pp. 583–588.
PLDI-1993-Adl-TabatabaiG #detection #scheduling: Detection and Recovery of Endangered Variables Caused by Instruction Scheduling (ARAT, TRG), pp. 13–25.
PLDI-1993-KernsE #latency #memory management #nondeterminism #scheduling: Balanced Scheduling: Instruction Scheduling When Memory Latency is Uncertain (DRK, SJE), pp. 278–289.
PLDI-1993-Pinter #approach #scheduling: Register Allocation with Instruction Scheduling: A New Approach (SSP), pp. 248–257.
Best-of-PLDI-1993-KernsE93a #latency #memory management #nondeterminism #scheduling: Balanced scheduling: instruction scheduling when memory latency is uncertain (with retrospective) (DRK, SJE), pp. 515–527.
HCI-SHI-1993-Lin #design #education: A Computer-Based Integrated Instruction and Design for Teaching Aesthetic Design (RL), pp. 748–753.
HCI-SHI-1993-SaitoTF: A Computer-Assisted Instruction System for Beginner’s Crude Charge Schedulers (KS, TT, KF), pp. 831–836.
ICML-1993-HuffmanL #interactive #learning #natural language: Learning Procedures from Interactive Natural Language Instructions (SBH, JEL), pp. 143–150.
DAC-1992-HuangD #compilation #pipes and filters #set #synthesis: High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers (IJH, AMD), pp. 135–140.
ESOP-1992-BernsteinRS #proving #safety: Proving Safety of Speculative Load Instructions at Compile Time (DB, MR, SS), pp. 56–72.
CHI-1992-Maulsby #interface #prototype: Prototyping an Instructible Interface: Moctec (DM), pp. 153–154.
CC-1992-ErtlK #pipes and filters #scheduling: Instruction Scheduling for Complex Pipelines (MAE, AK), pp. 207–218.
CC-1992-Griesemer #scheduling: Scheduling Instructions by Direct Placement (RG), pp. 229–235.
SEI-1991-FreemanRWKM #re-engineering: Instruction for Software Engineering Expertise (JTF, TRR, JSW, GAK, JDM), pp. 271–282.
PLDI-1991-BernsteinR #scheduling: Global Instruction Scheduling for Superscalar Machines (DB, MR), pp. 241–255.
PLDI-1991-BradleeHE #scheduling: The Marion System for Retargetable Instruction Scheduling (DGB, RRH, SJE), pp. 229–240.
PLDI-1991-McFarling: Procedure Merging with Instruction Caches (SM), pp. 71–79.
CHI-1991-Singley #named #programming #smalltalk: MOLEHILL: an instructional system for Smalltalk programming (MKS), pp. 439–440.
PLILP-1991-ErtlK #constraints #logic programming #scheduling #using: Optimal Instruction Scheduling using Constraint Logic Programming (MAE, AK), pp. 75–86.
ASPLOS-1991-BradleeEH #scheduling: Integrating Register Allocation and Instruction Scheduling for RISCs (DGB, SJE, RRH), pp. 122–131.
ASPLOS-1991-CmelikKDK #analysis #benchmark #metric #set #specification: An Analysis of SPARC and MIPS Instruction Set Utilization on the SPEC Benchmarks (RFC, SIK, DRD, EJK), pp. 290–302.
ASPLOS-1991-KatevenisT #branch #memory management: Reducing the Branch Penalty by Rearranging Instructions in Double-Width Memory (MK, NT), pp. 15–27.
ASPLOS-1991-Keppel #interface #on the fly: A Portable Interface for On-the-Fly Instruction Space Modifiction (DK), pp. 86–95.
ASPLOS-1991-Wall #parallel: Limits of Instruction-Level Parallelism (DWW), pp. 176–188.
ASPLOS-1991-WolfeS #architecture: A Variable Instruction Stream Extension to the VLIW Architecture (AW, JPS), pp. 2–14.
PLDI-1990-Sarkar #order #parallel: Instruction Reordering for Fork-Join Parallelism (VS), pp. 322–336.
CHI-1990-RossonCB #case study #smalltalk: Smalltalk scaffolding: a case study of minimalist instruction (MBR, JMC, RKEB), pp. 423–430.
POPL-1990-PalemS #scheduling: Scheduling Time-Critical Instructions on RISC Machines (KVP, BBS), pp. 270–280.
CC-1990-Kastens #compilation #parallel: Compilation for Instruction Parallel Processors (UK), pp. 26–41.
PPoPP-1990-Gupta #parallel: Employing Register Channels for the Exploitation of Instruction Level Parallelism (RG), pp. 118–127.
FPCA-1989-Argo: Improving the Three Instruction Machine (GA), pp. 100–115.
ML-1989-Diederich #learning: “Learning by Instruction” in connectionist Systems (JD), pp. 66–68.
ML-1989-Redmond #learning #reasoning: Combining Case-Based Reasoning, Explanation-Based Learning, and Learning form Instruction (MR), pp. 20–22.
ASPLOS-1989-AdamsZ #analysis #set #source code: An Analysis of 8086 Instruction Set Usage in MS DOS Programs (TLA, REZ), pp. 152–160.
ASPLOS-1989-CohnGLT #architecture #compilation #trade-off #word: Architecture and Compiler Tradeoffs for a Long Instruction Word Microprocessor (RC, TRG, MSL, PST), pp. 2–14.
ASPLOS-1989-JouppiW #parallel: Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines (NPJ, DWW), pp. 272–282.
ASPLOS-1989-McFarling #optimisation: Program Optimization for Instruction Caches (SM), pp. 183–191.
ASPLOS-1989-Mellor-CrummeyL: A Software Instruction Counter (JMMC, TJL), pp. 78–86.
ASPLOS-1989-SmithJH #multi: Limits on Multiple Instruction Issue (MDS, MJ, MH), pp. 290–302.
ASPLOS-1989-SohiV #architecture #design #trade-off: Tradeoffs in Instruction Format Design for Horizontal Architectures (GSS, SV), pp. 15–25.
DAC-1988-HenkelG #layout #named #set #verification: RISCE — A Reduced Instruction Set Circuit Extractor for Hierarchical VLSI Layout Verification (VH, UG), pp. 465–470.
JICSCP-1988-KurosawaYAB88 #architecture #performance #prolog: Instruction Architecture for a High Performance Integrated Prolog Processor IPP (KiK, SY, SA, TB), pp. 1506–1530.
ASPLOS-1987-DavidsonV #complexity #memory management #performance #set: The Effect of Instruction Set Complexity on Program Size and Memory Performance (JWD, RAV), pp. 60–64.
SLP-1987-KimuraC87 #set: An Abstract KL1 Machine and Its Instruction Set (YK, TC), pp. 468–477.
Best-of-PLDI-1986-MuchnickG #architecture #performance #pipes and filters #scheduling: Efficient instruction scheduling for a pipelined architecture (with retrospective) (SSM, PBG), pp. 167–174.
LFP-1986-SteenkisteH #lisp: LISP on a Reduced-Instruction-Set-Processor (PS, JLH), pp. 192–201.
ICLP-1986-Levy86 #automaton #haskell #set: A GHC Abstract Machine and Instruction Set (JL), pp. 157–171.
LFP-1984-WholeyF #design #lisp #set: The Design of an Instruction Set for Common Lisp (SW, SEF), pp. 150–158.
DAC-1983-HofmannL #approach #feature model #named: HEX: An instruction-driven approach to feature extraction (MH, UL), pp. 331–336.
SIGMOD-1982-Longstaff #named #query: ERQ: Controlled Inference and Instruction Techniques for DBMS Query Languages (JL), pp. 111–117.
SCC-1982-MorganR #code generation: Analyzing Exotic Instructions for a Retargetable Code Generator (TMM, LAR), pp. 197–204.
ASPLOS-1982-McDaniel #analysis #set #using: An Analysis of a Mesa Instruction Set Using Dynamic Instruction Frequencies (GM), pp. 167–176.
ASPLOS-1982-SweetS #analysis #empirical #set: Empirical Analysis of the Mesa Instruction Set (RES, JGSJ), pp. 158–166.
ASPLOS-1982-Wiecek #case study #compilation #execution #set: A Case Study of VAX-11 Instruction Set Usage for Compiler Execution (CAW), pp. 177–184.
DAC-1979-Barbacci #evaluation #set #simulation #specification #synthesis: Instruction set processor specifications for simulation, evaluation, and synthesis (MB), pp. 64–72.
DAC-1978-Dvorak #architecture #empirical: An experiment in architectural instruction (RWD), pp. 164–166.
SIGMOD-1978-NationsS #program analysis #sequence: Some DML Instruction Sequences for Application Program Analysis and Conversion (JN, SYWS), pp. 120–131.
DAC-1977-Smith #architecture #education: THE SITE MACHINE Computer-aided instruction in architectural education (EFS), pp. 266–274.
STOC-1977-PrabhalaS #comparison #set #stack: A Comparison of Instruction Sets for Stack Machines (BP, RS), pp. 132–142.
LISP-1963-Hart #lisp #metaprogramming: Macro Instructions for LISP (TH), p. 4.