BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
1 × Germany
1 × India
1 × Spain
1 × Sweden
4 × USA
Collaborated with:
D.Grund R.Wilhelm P.Backes S.Tripakis V.Touzeau C.Maïza D.Monniaux Andreas Abel 0002 S.Altmeyer C.Maiza S.Andalam A.Girault R.Sinha P.S.Roop D.N.Bui E.A.Lee I.Liu H.D.Patel C.Burguière J.Herter B.Wachter S.Wilhelm
Talks about:
analysi (7) cach (5) time (3) abstract (2) perform (2) system (2) replac (2) exact (2) microarchitectur (1) multiprocess (1)

Person: Jan Reineke

DBLP DBLP: Reineke:Jan

Contributed to:

VMCAI 20152015
DATE 20142014
TACAS 20142014
DAC 20132013
DAC 20112011
LCTES 20102010
VMCAI 20102010
SAS 20092009
LCTES 20082008
CAV (2) 20172017
POPL 20192019
ASPLOS 20192019

Wrote 12 papers:

VMCAI-2015-BackesR #abstraction #analysis #clustering #graph transformation #infinity
Analysis of Infinite-State Graph Transformation Systems by Cluster Abstraction (PB, JR), pp. 135–152.
DATE-2014-ReinekeW #performance #predict #resource management
Impact of resource sharing on performance and performance prediction (JR, RW), pp. 1–2.
TACAS-2014-ReinekeT #modelling #multi #problem
Basic Problems in Multi-View Modeling (JR, ST), pp. 217–232.
DAC-2013-AndalamGSRR #analysis #precise
Precise timing analysis for direct-mapped caches (SA, AG, RS, PSR, JR), p. 10.
DAC-2011-BuiLLPR #architecture #multi
Temporal isolation on multiprocessing architectures (DNB, EAL, IL, HDP, JR), pp. 274–279.
LCTES-2010-AltmeyerMR #analysis #bound
Resilience analysis: tightening the CRPD bound for set-associative caches (SA, CM, JR), pp. 153–162.
VMCAI-2010-WilhelmABGHRWW #analysis #realtime
Static Timing Analysis for Hard Real-Time Systems (RW, SA, CB, DG, JH, JR, BW, SW), pp. 3–22.
SAS-2009-GrundR #abstract interpretation
Abstract Interpretation of FIFO Replacement (DG, JR), pp. 120–136.
LCTES-2008-ReinekeG #analysis #policy
Relative competitive analysis of cache replacement policies (JR, DG), pp. 51–60.
CAV-2017-TouzeauMMR #analysis #nondeterminism #performance
Ascertaining Uncertainty for Efficient Exact Cache Analysis (VT, CM, DM, JR), pp. 22–40.
POPL-2019-TouzeauMMR #analysis #performance
Fast and exact analysis for LRU caches (VT, CM, DM, JR), p. 29.
ASPLOS-2019-0002R #architecture #latency #throughput Characterizing Latency, Throughput, and Port Usage of Instructions on Intel Microarchitectures (AA0, JR), pp. 673–686.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.