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Travelled to:
1 × USA
Collaborated with:
V.Popescu
Talks about:
processor (1) strategi (1) design (1) verif (1) sparc (1) reduc (1) innov (1) time (1) high (1) cycl (1)

Person: Bill McNamara

DBLP DBLP: McNamara:Bill

Contributed to:

DAC 19961996

Wrote 1 papers:

DAC-1996-PopescuM #design #verification
Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor (VP, BM), pp. 311–314.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.