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Collaborated with:
M.Kusano M.Wu C.Sung S.Guo L.Cheng Z.Yang T.Yu T.S.Zaman B.Paulsen J.Wang H.Eldib N.S.0001 S.K.Lahiri C.Enea J.Zhang P.Gao F.Song
Talks about:
modular (3) concurr (3) analysi (3) execut (3) countermeasur (2) interpret (2) abstract (2) softwar (2) channel (2) thread (2)

Person: Chao Wang 0001

DBLP DBLP: 0001:Chao_Wang

Contributed to:

FSE 20162016
ASE 20172017
ESEC/FSE 20172017
ASE 20182018
ESEC/FSE 20182018
ESEC/FSE 20192019
CAV (2) 20162016
CAV (2) 20182018
PLDI 20192019

Wrote 14 papers:

FSE-2016-Kusano0 #abstract interpretation #composition #thread
Flow-sensitive composition of thread-modular abstract interpretation (MK, CW0), pp. 799–809.
FSE-2016-SungKS0 #analysis #dependence #testing #web
Static DOM event dependency analysis for testing web applications (CS, MK, NS0, CW0), pp. 447–459.
ASE-2017-ChengYW #reduction #sequence #testing #user interface
Systematic reduction of GUI test sequences (LC, ZY, CW0), pp. 849–860.
ASE-2017-SungKW #composition #verification
Modular verification of interrupt-driven software (CS, MK, CW0), pp. 206–216.
ESEC-FSE-2017-GuoWW #execution #logic #programmable #symbolic computation
Symbolic execution of programmable logic controller code (SG, MW, CW0), pp. 326–336.
ESEC-FSE-2017-KusanoW #memory management #modelling #static analysis #thread
Thread-modular static analysis for relaxed memory models (MK, CW0), pp. 337–348.
ESEC-FSE-2017-YuZW #concurrent #named
DESCRY: reproducing system-level concurrency failures (TY, TSZ, CW0), pp. 694–704.
ASE-2018-SungLEW #concurrent #difference #scalability #semantics #source code
Datalog-based scalable semantic diffing of concurrent programs (CS, SKL, CE, CW0), pp. 656–666.
ASE-2018-SungPW #analysis #framework #named
CANAL: a cache timing analysis framework via LLVM transformation (CS, BP, CW0), pp. 904–907.
ESEC-FSE-2018-GuoWW #detection #execution #symbolic computation
Adversarial symbolic execution for detecting concurrency-related cache timing leaks (SG, MW, CW0), pp. 377–388.
ESEC-FSE-2019-WangSW #compilation
Mitigating power side channels during compilation (JW, CS, CW0), pp. 590–601.
CAV-2016-EldibWW #encryption #synthesis
Synthesis of Fault-Attack Countermeasures for Cryptographic Circuits (HE, MW, CW0), pp. 343–363.
CAV-2018-ZhangGSW #named #verification
SCInfer: Refinement-Based Verification of Software Countermeasures Against Side-Channel Attacks (JZ, PG, FS, CW0), pp. 157–177.
PLDI-2019-Wu0 #abstract interpretation #execution
Abstract interpretation under speculative execution (MW, CW0), pp. 802–815.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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