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Travelled to:
1 × Germany
1 × USA
Collaborated with:
C.Wang Y.Chen C.Huang Y.Lin D.Li T.Kuo S.Wu W.Tai W.Chang T.Chang
Talks about:
threshold (1) circuit (1) profil (1) rewir (1) minim (1) logic (1) encod (1) high (1) chip (1) avc (1)

Person: Chia-Chun Lin

DBLP DBLP: Lin:Chia=Chun

Contributed to:

DATE 20142014
DAC 20082008

Wrote 2 papers:

DATE-2014-LinWCH #logic
Rewiring for threshold logic circuit minimization (CCL, CYW, YCC, CYH), pp. 1–6.
DAC-2008-LinLLKWTCC
A 242mW, 10mm21080p H.264/AVC high profile encoder chip (YKL, DWL, CCL, TYK, SJW, WCT, WCC, TSC), pp. 78–83.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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