Travelled to:2 × France
2 × Germany
Collaborated with:Y.Chen C.Wang C.Chiang S.Datta V.Narayanan C.Lin W.Weng J.Chen C.Liu L.Tang H.Lin S.Chang H.Chou Y.Yang C.Shen
Talks about:transistor (2) synthesi (2) electron (2) circuit (2) analysi (2) singl (2) minim (2) array (2) use (2) probabilist (1)
Person: Ching-Yi Huang
DBLP: Huang:Ching=Yi
Contributed to:
2015201420132012Wrote 5 papers:
- DATE-2015-WengCCHW #using
- Using structural relations for checking combinationality of cyclic circuits (WCW, YCC, JHC, CYH, CYW), pp. 325–328.
- DATE-2014-LinWCH #logic
- Rewiring for threshold logic circuit minimization (CCL, CYW, YCC, CYH), pp. 1–6.
- DATE-2014-LiuCHWCDN #array #synthesis
- Width minimization in the Single-Electron Transistor array synthesis (CWL, CEC, CYH, CYW, YCC, SD, VN), pp. 1–4.
- DATE-2013-ChiangTWHCDN #array #configuration management #on the #order #synthesis #using
- On reconfigurable single-electron transistor arrays synthesis using reordering techniques (CEC, LFT, CYW, CYH, YCC, SD, VN), pp. 1807–1812.
- DATE-2012-LinWCCCHYS #analysis #functional #mutation testing #probability
- A probabilistic analysis method for functional qualification under Mutation Analysis (HYL, CYW, SCC, YCC, HMC, CYH, YCY, CCS), pp. 147–152.