Travelled to:1 × Germany
Collaborated with:C.Chiang C.Huang C.Wang Y.Chen S.Datta V.Narayanan
Talks about:transistor (1) synthesi (1) electron (1) width (1) singl (1) minim (1) array (1)
Person: Chian-Wei Liu
DBLP: Liu:Chian=Wei
Contributed to:
2014Wrote 1 papers:
- DATE-2014-LiuCHWCDN #array #synthesis
- Width minimization in the Single-Electron Transistor array synthesis (CWL, CEC, CYH, CYW, YCC, SD, VN), pp. 1–4.