Travelled to:1 × France
1 × Germany
Collaborated with:C.Huang C.Wang Y.Chen S.Datta V.Narayanan C.Liu L.Tang
Talks about:transistor (2) synthesi (2) electron (2) singl (2) array (2) reconfigur (1) techniqu (1) reorder (1) width (1) minim (1)
Person: Chang-En Chiang
DBLP: Chiang:Chang=En
Contributed to:
20142013Wrote 2 papers:
- DATE-2014-LiuCHWCDN #array #synthesis
- Width minimization in the Single-Electron Transistor array synthesis (CWL, CEC, CYH, CYW, YCC, SD, VN), pp. 1–4.
- DATE-2013-ChiangTWHCDN #array #configuration management #on the #order #synthesis #using
- On reconfigurable single-electron transistor arrays synthesis using reordering techniques (CEC, LFT, CYW, CYH, YCC, SD, VN), pp. 1807–1812.