BibSLEIGH — Vijaykrishnan

Travelled to:

1 × China
2 × Germany
3 × France
6 × USA

Collaborated with:

S.Datta Y.Xie S.Kestur J.Sampson A.K.Mishra K.M.Irick C.Wang Y.Chen K.Swaminathan M.S.Park M.J.Irwin N.Chandramoorthy X.Li Y.Xiao P.Singh D.L.Landis D.Dantara M.S.Kim A.Al-Maashri C.Chakrabarti C.Chiang C.Huang C.R.Das V.Saripalli M.Cotter K.Ma Y.Liu O.Tickoo R.Iyer D.Shin N.Chang J.Sabarad H.Liu G.Cauwenberghs D.M.Chiarulli S.P.Levitan P.Wong J.Zhan N.Stoimenov J.Ouyang L.Thiele Y.Chang Y.S.Huang M.Poremba C.King S.Eachempati S.Park C.Liu B.Sedighi R.Perricone L.Tang M.DeBole A.Jog C.Xu R.Iyer R.Das C.Nicopoulos D.Park R.R.Iyer M.S.Yousif Y.Zheng S.Li G.Tagliavini A.Pullini S.Advani S.A.Habsi J.Sampson L.Benini Mahmut Taylan Kandemir Jinyang Li 0002 T.Wu Zhibo Wang Y.X.0001

Talks about:

architectur (6) transistor (3) heterogen (3) electron (3) acceler (3) system (3) energi (3) effici (3) singl (3) optim (3)

Person: Vijaykrishnan Narayanan

DBLP: Narayanan:Vijaykrishnan

Contributed to:

2015

2014

2013

2012

2011

2008

2018

Wrote 21 papers:

DATE-2015-ParkTNII #performance #platform: Platform-aware dynamic configuration support for efficient text processing on heterogeneous system (MSP, OT, VN, MJI, RI), pp. 1503–1508.
HPCA-2015-ChandramoorthyT #architecture: Exploring architectural heterogeneity in intelligent vision systems (NC, GT, KMI, AP, SA, SAH, MC, JS, VN, LB), pp. 1–12.
HPCA-2015-MaZLSLLS0N #architecture #energy: Architecture exploration for ambient energy harvesting nonvolatile processors (KM, YZ, SL, KS, XL, YL, JS, YX, VN), pp. 526–537.
DAC-2014-SwaminathanLLKSN #architecture #paradigm: Steep Slope Devices: Enabling New Architectural Paradigms (KS, HL, XL, MSK, JS, VN), p. 6.
DATE-2014-LiuCHWCDN #array #synthesis: Width minimization in the Single-Electron Transistor array synthesis (CWL, CEC, CYH, CYW, YCC, SD, VN), pp. 1–4.
DATE-2014-NarayananDCCLW #using #video: Video analytics using beyond CMOS devices (VN, SD, GC, DMC, SPL, PW), pp. 1–5.
DATE-2014-SwaminathanKCSPSN #architecture #modelling: Modeling steep slope devices: From circuits to architectures (KS, MSK, NC, BS, RP, JS, VN), pp. 1–6.
DAC-2013-ZhanSOTNX #design #embedded #energy #optimisation #realtime: Designing energy-efficient NoC for real-time embedded systems through slack optimization (JZ, NS, JO, LT, VN, YX), p. 6.
DATE-2013-ChiangTWHCDN #array #configuration management #on the #order #synthesis #using: On reconfigurable single-electron transistor arrays synthesis using reordering techniques (CEC, LFT, CYW, CYH, YCC, SD, VN), pp. 1807–1812.
DATE-2013-XiaoINSC #power management: Saliency aware display power management (YX, KMI, VN, DS, NC), pp. 1203–1208.
HPCA-2013-ChangHPNXK #named #network: TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network (YYC, YSCH, MP, VN, YX, CTK), pp. 390–399.
DAC-2012-Al-MaashriDCCXNC #algorithm #recognition: Accelerating neuromorphic vision algorithms for recognition (AAM, MD, MC, NC, YX, VN, CC), pp. 579–584.
DAC-2012-JogMXXNID #architecture #performance: Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs (AJ, AKM, CX, YX, VN, RI, CRD), pp. 243–252.
DATE-2012-ParkKSNI #classification: An FPGA-based accelerator for cortical object classification (MSP, SK, JS, VN, MJI), pp. 691–696.
DATE-2012-SinghNL #generative #smt #testing: Hazard driven test generation for SMT processors (PS, VN, DLL), pp. 256–259.
DAC-2011-ChenEWDXN #array #automation #configuration management: Automated mapping for reconfigurable single-electron transistor arrays (YCC, SE, CYW, SD, YX, VN), pp. 878–883.
DAC-2011-KesturIPANC #architecture #co-evolution #design #framework #re-engineering #using: An algorithm-architecture co-design framework for gridding reconstruction using FPGAs (SK, KMI, SP, AAM, VN, CC), pp. 585–590.
DAC-2011-SaripalliMDN #energy #hybrid: An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores (VS, AKM, SD, VN), pp. 729–734.
DATE-2011-KesturDN #named #streaming: SHARC: A streaming model for FPGA accelerators and its application to Saliency (SK, DD, VN), pp. 1237–1242.
HPCA-2008-DasMNPNIYD #architecture #optimisation #performance: Performance and power optimization through data compression in Network-on-Chip architectures (RD, AKM, CN, DP, VN, RRI, MSY, CRD), pp. 215–225.
ASPLOS-2018-MaLKSN0WWL0 #named #optimisation: NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing (KM, XL, MTK, JS, VN, JL0, TW, ZW, YL, YX0), pp. 782–796.