BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
2 × USA
Collaborated with:
R.G.Melhem A.K.Jones S.Chang Z.Zhang P.Maresca V.Ternelli
Talks about:
multiprocessor (1) interconnect (1) transform (1) prototyp (1) design (1) critic (1) applic (1) rapid (1) model (1) autom (1)

Person: Colin J. Ihrig

DBLP DBLP: Ihrig:Colin_J=

Contributed to:

DAC 20102010
SEKE 20082008

Wrote 2 papers:

DAC-2010-IhrigMJ #automation #design #manycore #modelling
Automated modeling and emulation of interconnect designs for many-core chip multiprocessors (CJI, RGM, AKJ), pp. 431–436.
SEKE-2008-ChangZIMT #agile #prototype
Transformations for Rapid Prototyping of Time-critical Applications (SKC, ZZ, CJI, PM, VT), pp. 4–15.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.