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Collaborated with:
L.N.Vintan G.B.Steven
Talks about:
superscalar (1) processor (1) instruct (1) organis (1) impact (1) rate (1) issu (1) cach (1)

Person: Cristian Armat

DBLP DBLP: Armat:Cristian

Contributed to:

PDP 19991999

Wrote 1 papers:

PDP-1999-VintanAS
The impact of cache organisation on the instruction issue rate of a superscalar processor (LNV, CA, GBS), pp. 58–65.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.