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Collaborated with:
L.N.Vintan C.Armat R.Adams S.M.Gray
Talks about:
instruct (2) issu (2) superscalar (1) architectur (1) processor (1) schedul (1) organis (1) multipl (1) static (1) impact (1)

Person: Gordon B. Steven

DBLP DBLP: Steven:Gordon_B=

Contributed to:

PDP 19991999
PDP 19941994

Wrote 2 papers:

PDP-1999-VintanAS
The impact of cache organisation on the instruction issue rate of a superscalar processor (LNV, CA, GBS), pp. 58–65.
PDP-1994-AdamsGS #architecture #compilation #multi #named
Harp: A Statically Scheduled Multiple-instruction Issue Architecture And Its Compiler (RA, SMG, GBS), pp. 76–81.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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