Travelled to:1 × France
2 × Germany
Collaborated with:C.Metra M.Omaña C.Steiner N.Timoncini M.Spica J.M.Cazeaux
Talks about:high (4) reliabl (2) analysi (2) code (2) interconnect (1) transient (1) implement (1) crosstalk (1) parallel (1) detector (1)
Person: Daniele Rossi
DBLP: Rossi:Daniele
Contributed to:
201120062003Wrote 4 papers:
- DATE-2011-RossiTSM #analysis #fault #memory management #performance #reliability
- Error correcting code analysis for cache memory high reliability and performance (DR, NT, MS, CM), pp. 1620–1625.
- DATE-2006-OmanaCRM #detection #fault #low cost #reliability
- Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects (MO, JMC, DR, CM), pp. 170–175.
- DATE-2006-RossiSM #analysis
- Analysis of the impact of bus implemented EDCs on on-chip SSN (DR, CS, CM), pp. 59–64.
- DATE-2003-OmanaRM #parallel
- High Speed and Highly Testable Parallel Two-Rail Code Checker (MO, DR, CM), pp. 10608–10615.