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Travelled to:
1 × Portugal
7 × USA
Collaborated with:
H.Chen S.Ghanta I.Lin K.C.Chang L.Liu S.H.Yen S.Cheng R.J.Enbody S.H.Yen H.C.Yen J.F.Naveda C.Chang R.C.T.Lee A.Lim P.Hsu Y.Chang P.Huang T.Kuo A.Raghuveer M.Jindal M.F.Mokbel B.K.Debnath
Talks about:
path (7) algorithm (3) perform (3) analysi (3) effici (3) critic (3) optim (3) time (3) approach (2) problem (2)

Person: David Hung-Chang Du

DBLP DBLP: Du:David_Hung=Chang

Contributed to:

DAC 20112011
CIKM 20072007
DAC 19921992
DAC 19911991
DAC 19901990
DAC 19891989
DAC 19881988
DAC 19861986
SIGMOD 19801980

Wrote 15 papers:

DAC-2011-HsuCHKD #file system #reliability
A version-based strategy for reliability enhancement of flash file systems (PHH, YHC, PCH, TWK, DHCD), pp. 29–34.
CIKM-2007-RaghuveerJMDD #approach #performance #semistructured data #towards
Towards efficient search on unstructured data: an intelligent-storage approach (AR, MJ, MFM, BKD, DHCD), pp. 951–954.
Circuit Enhancement by Eliminating Long False Paths (HCC, DHCD, SWC), pp. 249–252.
DAC-1992-ChengCDL #optimisation #performance
The Role of Long and Short Paths in Circuit Performance Optimization (SWC, HCC, DHCD, AL), pp. 543–548.
DAC-1991-ChenDL #optimisation #performance
Critical Path Selection for Performance Optimization (HCC, DHCD, LRL), pp. 547–550.
DAC-1991-LiuDC #algorithm #parallel #performance
An Efficient Parallel Critical Path Algorithm (LRL, DHCD, HCC), pp. 535–540.
Performance-Driven Constructive Placement (IL, DHCD), pp. 103–106.
DAC-1989-DuYG #analysis #on the #problem
On the General False Path Problem in Timing Analysis (DHCD, SHY, SG), pp. 555–560.
DAC-1989-LinDY #2d #layout #matrix #synthesis
Gate Matrix Layout Synthesis with Two-Dimensional Folding (IL, DHCD, SHCY), pp. 37–42.
DAC-1989-YenDG #algorithm #analysis #performance
Efficient Algorithms for Extracting the K most Critical Paths in Timing Analysis (SHY, DHCD, SG), pp. 649–654.
DAC-1988-YenGD #algorithm #analysis
A Path Selection Algorithm for Timing Analysis (HCY, SG, DHCD), pp. 720–723.
DAC-1986-ChangD #preprocessor #problem
A preprocessor for the via minimization problem (KCC, DHCD), pp. 702–707.
Near-optimal n-layer channel routing (RJE, DHCD), pp. 708–714.
DAC-1986-NavedaCD #approach #multi
A new approach to multi-layer PCB routing with short vias (JFN, KCC, DHCD), pp. 696–701.
Some Properties of Cartesian Product Files (CCC, RCTL, DHCD), pp. 157–168.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.