Travelled to:1 × The Netherlands
2 × USA
Collaborated with:C.Eisner D.Fisman J.Havlicek A.McIsaac T.N.Mudge J.P.Hayes Y.Lustig
Talks about:tempor (2) microprocessor (1) truncat (1) pipelin (1) generat (1) definit (1) reason (1) design (1) verif (1) logic (1)
Person: David Van Campenhout
DBLP: Campenhout:David_Van
Contributed to:
2003
2003
1999Wrote 3 papers:
- CAV-2003-EisnerFHLMC #logic #reasoning
- Reasoning with Temporal Logic on Truncated Paths (CE, DF, JH, YL, AM, DVC), pp. 27–39.
- ICALP-2003-EisnerFHMC
- The Definition of a Temporal Clock Operator (CE, DF, JH, AM, DVC), pp. 857–870.
- DAC-1999-CampenhoutMH #design #generative #pipes and filters #testing #verification
- High-Level Test Generation for Design Verification of Pipelined Microprocessors (DVC, TNM, JPH), pp. 185–188.