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Travelled to:
1 × Canada
6 × USA
Collaborated with:
N.P.Jouppi A.Srivastava M.L.Powell J.Bertoni
Talks about:
regist (5) retrospect (3) alloc (3) use (3) architectur (2) parallel (2) instruct (2) behavior (2) program (2) predict (2)

Person: David W. Wall

DBLP DBLP: Wall:David_W=

Facilitated 1 volumes:

PLDI 1995Ed

Contributed to:

PLDI 19941994
ASPLOS 19911991
Best of PLDI 20041991
PLDI 19911991
ASPLOS 19891989
Best of PLDI 20041988
PLDI 19881988
ASPLOS 19871987
Best of PLDI 20041986
POPL 19821982

Wrote 11 papers:

PLDI-1994-SrivastavaW #architecture #optimisation
Link-Time Optimization of Address Calculation on a 64-bit Architecture (AS, DWW), pp. 49–60.
ASPLOS-1991-Wall #parallel
Limits of Instruction-Level Parallelism (DWW), pp. 176–188.
Best-of-PLDI-1991-Wall91a #behaviour #predict #using
Predicting program behavior using real or estimated profiles (with retrospective) (DWW), pp. 429–441.
PLDI-1991-Wall #behaviour #predict #using
Predicting Program Behavior Using Real or Estimated Profiles (DWW), pp. 59–70.
ASPLOS-1989-JouppiBW #architecture #float
A Unified Vector/Scalar Floating-Point Architecture (NPJ, JB, DWW), pp. 134–143.
ASPLOS-1989-JouppiW #parallel
Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines (NPJ, DWW), pp. 272–282.
Best-of-PLDI-1988-Wall88a
Register windows vs. register allocation (with retrospective) (DWW), pp. 270–282.
PLDI-1988-Wall
Register Windows versus Register Allocation (DWW), pp. 67–78.
ASPLOS-1987-WallP #experience #using
The Mahler Experience: Using and Intermediate Language as the Machine Description (DWW, MLP), pp. 100–104.
Best-of-PLDI-1986-Wall
Global register allocation at link time (with retrospective) (DWW), pp. 192–204.
POPL-1982-Wall
Messages as Active Agents (DWW), pp. 34–39.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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