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Travelled to:
1 × China
1 × Germany
11 × USA
2 × France
Collaborated with:
∅ D.W.Wall N.Muralimanohar Y.Xie P.Ranganathan K.I.Farkas P.Chow X.Dong C.Xu S.Borkar P.Stenström J.Collard S.Yehia J.Bertoni J.Wang D.Niu N.Chatterjee R.Balasubramonian A.Davis J.L.Hennessy F.Baskett T.R.Gross J.Gill K.Chen S.Li J.H.Ahn J.B.Brockman D.H.Yoon J.Chang M.Erez
Talks about:
memori (4) architectur (3) design (3) level (3) dram (3) non (3) processor (2) volatil (2) perform (2) implic (2)

Person: Norman P. Jouppi

DBLP DBLP: Jouppi:Norman_P=

Contributed to:

DAC 20132013
HPCA 20132013
DATE 20122012
HPCA 20122012
DATE 20112011
HPCA 20112011
DATE 20072007
HPCA 20052005
PPoPP 20052005
CSCW 20022002
HPCA 19961996
HPCA 19951995
ASPLOS 19891989
DAC 19831983
ASPLOS 19821982

Wrote 16 papers:

DAC-2013-XuNMJX #comprehension #design #memory management #multi #trade-off
Understanding the trade-offs in multi-level cell ReRAM memory design (CX, DN, NM, NPJ, YX), p. 6.
HPCA-2013-WangDXJ #named
i2WAP: Improving non-volatile cache lifetime by reducing inter- and intra-set write variations (JW, XD, YX, NPJ), pp. 234–245.
DATE-2012-ChenLMABJ #3d #architecture #in memory #memory management #modelling #named
CACTI-3DD: Architecture-level modeling for 3D die-stacked DRAM main memory (KC, SL, NM, JHA, JBB, NPJ), pp. 33–38.
HPCA-2012-ChatterjeeMBDJ #staged
Staged Reads: Mitigating the impact of DRAM writes on DRAM reads (NC, NM, RB, AD, NPJ), pp. 41–52.
DATE-2011-XuDJX #design
Design implications of memristor-based RRAM cross-point structures (CX, XD, NPJ, YX), pp. 734–739.
HPCA-2011-YoonMCRJE #fault #memory management #named
FREE-p: Protecting non-volatile memory against both hard and soft errors (DHY, NM, JC, PR, NPJ, ME), pp. 466–477.
DATE-2007-BorkarJS #integration
Microprocessors in the era of terascale integration (SB, NPJ, PS), pp. 237–242.
HPCA-2005-RanganathanJ #architecture #enterprise #research #roadmap
Enterprise IT Trends and Implications for Architecture Research (PR, NPJ), pp. 253–256.
PPoPP-2005-CollardJY #memory management #monitoring #optimisation #performance
System-wide performance monitors and their application to the optimization of coherent memory accesses (JFC, NPJ, SY), pp. 247–254.
CSCW-2002-Jouppi #mobile #towards
First steps towards mutually-immersive mobile telepresence (NPJ), pp. 354–363.
HPCA-1996-FarkasJC #design
Register File Design Considerations in Dynamically Scheduled Processors (KIF, NPJ, PC), pp. 40–51.
HPCA-1995-FarkasJC #execution #how #multi #question
How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? (KIF, NPJ, PC), pp. 78–89.
ASPLOS-1989-JouppiBW #architecture #float
A Unified Vector/Scalar Floating-Point Architecture (NPJ, JB, DWW), pp. 134–143.
ASPLOS-1989-JouppiW #parallel
Available Instruction-Level Parallelism for Superscalar and Superpipelined Machines (NPJ, DWW), pp. 272–282.
DAC-1983-Jouppi #analysis
Timing analysis for nMOS VLSI (NPJ), pp. 411–418.
ASPLOS-1982-HennessyJBGG #hardware #performance #trade-off
Hardware/Software Tradeoffs for Increased Performance (JLH, NPJ, FB, TRG, JG), pp. 2–11.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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