BibSLEIGH corpus
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Travelled to:
4 × USA
Collaborated with:
E.G.Ulrich R.K.Cleghorn M.H.Doshi R.B.Sullivan T.E.Baker S.P.Bryant
Talks about:
simul (4) circuit (2) logic (2) digit (2) placement (1) interact (1) hierarch (1) generat (1) concurr (1) cluster (1)

Person: Donald M. Schuler

DBLP DBLP: Schuler:Donald_M=

Contributed to:

DAC 19841984
DAC 19771977
DAC 19751975
DAC 19721972

Wrote 4 papers:

DAC-1984-DoshiSS #interactive #logic #multi
THEMIS logic simulator — a mix mode, multi-level, hierarchical, interactive digital circuit simulator (MHD, RBS, DMS), pp. 24–31.
DAC-1977-SchulerC #fault #performance #simulation
An efficient method of fault simulation for digital circuits modeled from boolean gates and memories (DMS, RKC), pp. 230–238.
DAC-1975-SchulerUBB #concurrent #generative #logic #random testing #simulation #testing #using
Random test generation using concurrent logic simulation (DMS, EGU, TEB, SPB), pp. 261–267.
DAC-1972-SchulerU #clustering #linear
Clustering and linear placement (DMS, EGU), pp. 50–56.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.