Travelled to:1 × France
1 × Germany
1 × Italy
1 × Portugal
1 × The Netherlands
1 × United Kingdom
3 × USA
Collaborated with:M.Y.Vardi Y.Abarbanel V.Rusu D.Harel S.Baartmans A.Pnueli M.Siegel T.Arons E.Elster J.Shalev R.Sebastiani S.Tonetta S.Ozer L.Fix S.Mador-Haim A.Tiemeyer M.Mishaeli L.D.Zuck R.Armoni A.Flaisher R.Gerth B.Ginsburg T.Kanza A.Landver Y.Zbar
Talks about:valid (3) logic (3) properti (2) tempor (2) prove (2) elementari (1) translat (1) transact (1) microcod (1) challeng (1)
Person: Eli Singerman
DBLP: Singerman:Eli
Contributed to:
20142011
2008
20052004
200219991998
1997Wrote 9 papers:
- DAC-2014-AbarbanelSV #challenge #validation
- Validation of SoC Firmware-Hardware Flows: Challenges and Solution Directions (YA, ES, MYV), p. 4.
- DAC-2011-SingermanAB #transaction #validation
- Transaction based pre-to-post silicon validation (ES, YA, SB), pp. 564–568.
- DATE-2008-AronsEOSS #low level #performance #simulation
- Efficient Symbolic Simulation of Low Level Software (TA, EE, SO, JS, ES), pp. 825–830.
- CAV-2005-AronsEFMMSSTVZ #verification
- Formal Verification of Backward Compatibility of Microcode (TA, EE, LF, SMH, MM, JS, ES, AT, MYV, LDZ), pp. 185–198.
- CAV-2004-SebastianiSTV #model checking
- GSTE Is Partitioned Model Checking (RS, ES, ST, MYV), pp. 229–241.
- TACAS-2002-ArmoniFFGGKLMSTVZ #logic
- The ForSpec Temporal Logic: A New Temporal Property-Specification Language (RA, LF, AF, RG, BG, TK, AL, SMH, ES, AT, MYV, YZ), pp. 296–211.
- TACAS-1999-RusuS #abstraction #on the #proving #safety #static analysis #theorem proving
- On Proving Safety Properties by Integrating Static Analysis, Theorem Proving and Abstraction (VR, ES), pp. 178–192.
- TACAS-1998-PnueliSS #validation
- Translation Validation (AP, MS, ES), pp. 151–166.
- ICALP-1997-HarelS #logic #process
- Computation Paths Logic: An Expressive, yet Elementary, Process Logic (abridged version) (DH, ES), pp. 408–418.