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Travelled to:
2 × France
2 × USA
Collaborated with:
K.Lampaert H.Zhu I.I.Luican Y.Pang C.Cheng H.Gräb R.Castro-López Y.Chang F.V.Fernández M.P.Lin M.Strasser
Talks about:
represent (2) placement (2) layout (2) analog (2) constraint (1) dimension (1) synthesi (1) symmetri (1) hierarch (1) approach (1)

Person: Florin Balasa

DBLP DBLP: Balasa:Florin

Contributed to:

DATE 20092009
DATE 20072007
DAC 20002000
DAC 19991999

Wrote 4 papers:

DATE-2009-GrabBCCFLS #layout #synthesis
Analog layout synthesis — Recent advances in topological approaches (HG, FB, RCL, YWC, FVF, MPHL, MS), pp. 274–279.
DATE-2007-ZhuLB #memory management #multi
Mapping multi-dimensional signals into hierarchical memory organizations (HZ, IIL, FB), pp. 385–390.
DAC-2000-PangBLC #constraints #representation #symmetry
Block placement with symmetry constraints based on the O-tree non-slicing representation (YP, FB, KL, CKC), pp. 464–467.
DAC-1999-BalasaL #layout #representation #using
Module Placement for Analog Layout Using the Sequence-Pair Representation (FB, KL), pp. 274–279.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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