Travelled to:1 × France
2 × Germany
Collaborated with:∅ D.Müller-Gritschneder F.Balasa R.Castro-López Y.Chang F.V.Fernández M.P.Lin M.Strasser E.Barke D.Grabowski L.Hedrich S.Heinen R.Popp S.Steinhorst Y.Wang
Talks about:analog (4) approach (3) circuit (2) synthesi (1) challeng (1) topolog (1) specif (1) recent (1) pareto (1) layout (1)
Person: Helmut Gräb
DBLP: Gr=auml=b:Helmut
Contributed to:
201220102009Wrote 4 papers:
- DATE-2012-Graeb #challenge
- ITRS 2011 Analog EDA Challenges and Approaches (HG), pp. 1150–1155.
- DATE-2010-Mueller-GritschnederG #specification
- Computation of yield-optimized Pareto fronts for analog integrated circuit specifications (DMG, HG), pp. 1088–1093.
- DATE-2009-BarkeGGHHPSW #formal method #verification
- Formal approaches to analog circuit verification (EB, DG, HG, LH, SH, RP, SS, YW), pp. 724–729.
- DATE-2009-GrabBCCFLS #layout #synthesis
- Analog layout synthesis — Recent advances in topological approaches (HG, FB, RCL, YWC, FVF, MPHL, MS), pp. 274–279.