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Travelled to:
5 × France
5 × Germany
Collaborated with:
Á.Rodríguez-Vázquez E.Roca R.Castro-López F.Medeiro G.Dündar O.Guerra A.Unutulmaz B.Liu G.G.E.Gielen M.Velasco-Jimenez R.Castro-López M.Delgado-Restituto I.Garcia-Vargas M.Galan E.Afacan S.Ay I.F.Baskaya F.M.Pérez-Montes R.Domínguez-Castro J.D.Rodríguez-García H.Gräb F.Balasa Y.Chang M.P.Lin M.Strasser J.Ruiz-Amaya J.L.d.l.Rosa R.d.Río M.B.Pérez-Verdú
Talks about:
analog (7) circuit (4) base (4) hierarch (3) optim (3) model (3) synthesi (2) approach (2) generat (2) analysi (2)

Person: Francisco V. Fernández

DBLP DBLP: Fern=aacute=ndez:Francisco_V=

Contributed to:

DATE 20142014
DATE 20132013
DATE 20102010
DATE 20092009
DATE DF 20042004
DATE 20032003
DATE 20012001
DATE 20002000
DATE 19991999
ED&TC 19971997

Wrote 12 papers:

DATE-2014-AfacanAFDB #automation #design #modelling #optimisation
Model based hierarchical optimization strategies for analog design automation (EA, SA, FVF, GD, IFB), pp. 1–4.
DATE-2014-Velasco-JimenezCRF #composition #implementation #modelling #performance
Implementation issues in the hierarchical composition of performance models of analog circuits (MVJ, RCL, ER, FVF), pp. 1–6.
DATE-2013-UnutulmazDF #optimisation #using
Area optimization on fixed analog floorplans using convex area functions (AU, GD, FVF), pp. 1843–1848.
DATE-2010-LiuFG #optimisation #performance
An accurate and efficient yield optimization method for analog circuits based on computing budget allocation and memetic search technique (BL, FVF, GGEG), pp. 1106–1111.
DATE-2009-GrabBCCFLS #layout #synthesis
Analog layout synthesis — Recent advances in topological approaches (HG, FB, RCL, YWC, FVF, MPHL, MS), pp. 274–279.
DATE-DF-2004-Ruiz-AmayaRMFRPR #matlab #synthesis
MATLAB/SIMULINK-Based High-Level Synthesis of Discrete-Time and Continuous-Time [Sigma, Delta] Modulators (JRA, JLdlR, FM, FVF, RdR, MBPV, ÁRV), pp. 150–155.
DATE-2003-Castro-LopezFMR #behaviour #hardware #modelling #simulation #using
Behavioural Modelling and Simulation of SigmaDelta Modulators Using Hardware Description Languages (RCL, FVF, FM, ÁRV), pp. 10168–10175.
Retargeting of mixed-signal blocks for SoCs (RCL, FVF, MDR, ÁRV), pp. 772–775.
DATE-2000-GuerraRFR #analysis #approach #scalability
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits (OG, ER, FVF, ÁRV), pp. 48–52.
DATE-2000-Perez-MontesMDFR #named
XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool (FMPM, FM, RDC, FVF, ÁRV), p. 739.
DATE-1999-GuerraRRFR #fault #generative
An Accurate Error Control Mechanism for Simplification Before Generation Algorihms (OG, JDRG, ER, FVF, ÁRV), p. 412–?.
EDTC-1997-Garcia-VargasGFR #algorithm #analysis #generative #scalability
An algorithm for numerical reference generation in symbolic analysis of large analog circuits (IGV, MG, FVF, ÁRV), pp. 395–399.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.