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Travelled to:
1 × France
1 × USA
Collaborated with:
Y.Huang R.Tsay Y.Lu F.Yu B.Zeng C.Lee
Talks about:
synchron (2) simul (2) time (2) determinist (1) interfac (1) instruct (1) approach (1) section (1) hardwar (1) intrus (1)

Person: Hsin-I. Wu

DBLP DBLP: Wu:Hsin=I=

Contributed to:

DATE 20132013
DAC 20122012

Wrote 2 papers:

DATE-2013-YuZHWLT #approach #manycore #set #simulation
A critical-section-level timing synchronization approach for deterministic multi-core instruction set simulations (FWY, BHZ, YHH, HIW, CRL, RST), pp. 643–648.
DAC-2012-HuangLWT #interface
A non-intrusive timing synchronization interface for hardware-assisted HW/SW co-simulation (YHH, YSL, HIW, RST), pp. 127–132.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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