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Travelled to:
1 × USA
Collaborated with:
S.Cromar D.Chen
Talks about:
algorithm (1) target (1) reduct (1) glitch (1) power (1) level (1) estim (1) high (1) fpga (1) bind (1)

Person: Jaeho Lee

DBLP DBLP: Lee:Jaeho

Contributed to:

DAC 20092009

Wrote 1 papers:

DAC-2009-CromarLC #algorithm #reduction
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation (SC, JL, DC), pp. 838–843.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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