BibSLEIGH — Deming

Travelled to:

2 × Germany
3 × France
8 × USA

Collaborated with:

Y.Chen L.Cheng M.D.F.Wong J.Cong C.Dong K.A.Campbell Y.Liang L.Wan A.Sangai W.W.Hwu Y.Liang Z.Sun C.Wei A.Dhar C.Lin S.Cromar J.Lee S.Chilstedt J.Y.Lin D.Lin S.Mitra P.Vissa D.Z.Pan M.Gholipour Y.Fan J.Xu L.Deng A.Ramachandran Y.Heo J.Ma A.Papakonstantinou A.Rogachev G.Iannaccone G.Fiori Z.Cui S.Zhao K.Rupnow Y.Zhang D.L.Jones B.Greskamp U.R.Karpuzcu J.J.Cook J.Torrellas C.B.Zilles

Talks about:

power (6) synthesi (5) optim (5) level (5) high (5) fpga (5) reduct (3) glitch (3) design (3) spice (3)

Person: Deming Chen

DBLP: Chen:Deming

Contributed to:

2015

2014

2013

2012

2010

2009

2007

2006

Wrote 20 papers:

DAC-2015-CampbellLMC #debugging #detection #fault #hybrid #synthesis #using #validation: Hybrid quick error detection (H-QED): accelerator validation and debug using high-level synthesis principles (KAC, DL, SM, DC), p. 6.
DAC-2015-CampbellVPC #detection #fault #low cost #synthesis: High-level synthesis of error detecting cores through low-cost modulo-3 shadow datapaths (KAC, PV, DZP, DC), p. 6.
DAC-2015-ChenSC #flexibility: A SPICE model of flexible transition metal dichalcogenide field-effect transistors (YYC, ZS, DC), p. 6.
DATE-2015-RamachandranHHM #fault: FPGA accelerated DNA error correction (AR, YH, WmWH, JM, DC), pp. 1371–1376.
DATE-2015-WeiDC #architecture #memory management #multi #scalability: A scalable and high-density FPGA architecture with multi-level phase change memory (CW, AD, DC), pp. 1365–1370.
DAC-2014-LiangC #analysis #clustering #named #network #probability #reduction #scalability #smarttech: ClusRed: Clustering and Network Reduction Based Probabilistic Optimal Power Flow Analysis for Large-Scale Smart Grids (YL, DC), p. 6.
DAC-2014-LinWC #data mining #design #logic #mining #named #power management #synthesis: C-Mine: Data Mining of Logic Common Cases for Low Power Synthesis of Better-Than-Worst-Case Designs (CHL, LW, DC), p. 6.
DATE-2014-GholipourCSC #modelling #scalability: Highly accurate SPICE-compatible modeling for single- and double-gate GNRFETs with studies on technology scaling (MG, YYC, AS, DC), pp. 1–6.
DAC-2013-PapakonstantinouCHCL #kernel #migration: Throughput-oriented kernel porting onto FPGAs (AP, DC, WmWH, JC, YL), p. 10.
DATE-2013-ChenRSIFC #analysis #process: A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation (YYC, AR, AS, GI, GF, DC), pp. 1789–1794.
DATE-2012-LiangCZRZJC #3d #implementation #locality #optimisation #performance #realtime: Real-time implementation and performance optimization of 3D sound localization on GPUs (YL, ZC, SZ, KR, YZ, DLJ, DC), pp. 832–835.
DAC-2010-ChenDC #synthesis: Clock tree synthesis under aggressive buffer insertion (YYC, CD, DC), pp. 86–89.
DAC-2009-CromarLC #algorithm #reduction: FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation (SC, JL, DC), pp. 838–843.
DATE-2009-DongCC #configuration management #design: Reconfigurable circuit design with nanomaterials (CD, SC, DC), pp. 442–447.
HPCA-2009-GreskampWKCTCZ #design #named: Blueshift: Designing processors for timing speculation from the ground up (BG, LW, URK, JJC, JT, DC, CBZ), pp. 213–224.
DAC-2007-ChengCW #named #power management: GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches (LC, DC, MDFW), pp. 318–323.
DAC-2007-ChengCW07a #named #synthesis: DDBDD: Delay-Driven BDD Synthesis for FPGAs (LC, DC, MDFW), pp. 910–915.
DAC-2006-ChenCFX #multi: Optimality study of resource binding with multi-Vdds (DC, JC, YF, JX), pp. 580–585.
DAC-2006-ChengDCW #algorithm #generative #performance #power management #reduction: A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction (LC, LD, DC, MDFW), pp. 117–120.
DAC-2006-LinCC #clustering #optimisation: Optimal simultaneous mapping and clustering for FPGA delay optimization (JYL, DC, JC), pp. 472–477.