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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
2 × USA
Collaborated with:
T.Kim C.Liu J.Seo
Talks about:
techniqu (1) synthesi (1) procedur (1) testabl (1) stepwis (1) schedul (1) circuit (1) voltag (1) static (1) sensit (1)

Person: Ki-Seok Chung

DBLP DBLP: Chung:Ki=Seok

Contributed to:

DAC 20042004
DAC 20012001

Wrote 3 papers:

DAC-2004-SeoKC #realtime #scheduling
Profile-based optimal intra-task voltage scheduling for hard real-time applications (JS, TK, KSC), pp. 87–92.
DAC-2001-KimCL #estimation #logic
A Static Estimation Technique of Power Sensitivity in Logic Circuits (TK, KSC, CLL), pp. 215–219.
EDAC-1994-KimCL #refinement #synthesis #testing
A Stepwise Refinement Data Path Synthesis Procedure for Easy Testability (TK, KSC, CLL), pp. 586–590.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.