BibSLEIGH — Proceedings of the 38th Design Automation Conference

Proceedings of the 38th Design Automation Conference
DAC, 2001.

SYS

@proceedings{DAC-2001,
	acmid         = "378239",
	address       = "Las Vegas, Nevada, USA",
	isbn          = "1-58113-297-2",
	publisher     = "{ACM}",
	title         = "{Proceedings of the 38th Design Automation Conference}",
	year          = 2001,
}

Contents (153 items)

DAC-2001-SylvesterK #challenge #design #performance: Future Performance Challenges in Nanometer Design (DS, HK), pp. 3–8.
DAC-2001-Maly #design: IC Design in High-Cost Nanometer-Technologies Era (WM), pp. 9–14.
DAC-2001-LahiriRL #architecture #communication #design #named: LOTTERYBUS: A New High-Performance Communication Architecture for System-on-Chip Designs (KL, AR, GL), pp. 15–20.
DAC-2001-ChelceaN #interface #protocol #robust: Robust Interfaces for Mixed-Timing Systems with Application to Latency-Insensitive Protocols (TC, SMN), pp. 21–26.
DAC-2001-MeguerdichianDK #design #multi: Latency-Driven Design of Multi-Purpose Systems-On-Chip (SM, MD, DK), pp. 27–30.
DAC-2001-SanghaviW #estimation #power of: Estimation of Speed, Area, and Power of Parameterizable, Soft IP (JVS, AW), pp. 31–34.
DAC-2001-WangHLKZMD #abstraction #hybrid #refinement #simulation #verification: Formal Property Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines (DW, PHH, JL, JHK, YZ, HKTM, RFD), pp. 35–40.
DAC-2001-MneimnehAWCSA #hybrid #scalability #verification: Scalable Hybrid Verification of Complex Microprocessors (MNM, FAA, CTW, SC, KAS, TMA), pp. 41–46.
DAC-2001-KolblKD #simulation: Symbolic RTL Simulation (AK, JHK, RFD), pp. 47–52.
DAC-2001-Dervisoglu #architecture #data access: A Unified DFT Architecture for Use with IEEE 1149.1 and VSIA/IEEE P1500 Compliant Test Access Controllers (BID), pp. 53–58.
DAC-2001-LaiC #testing: Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip (WCL, KTC), pp. 59–64.
DAC-2001-OckunzziP #algorithm: Test Strategies for BIST at the Algorithmic and Register-Transfer Levels (KAO, CAP), pp. 65–70.
DAC-2001-GrobmanTWYTD #challenge #design #physics: Reticle Enhancement Technology: Implications and Challenges for Physical Design (WG, MT, RW, CY, RT, ED), pp. 73–78.
DAC-2001-LiebmannLHG #design #logic: Enabling Alternating Phase Shifted Mask Designs for a Full Logic Gate Level: Design Rules and Design Rule Checking (LL, JL, FLH, IG), pp. 79–84.
DAC-2001-RiegerMP #design #layout: Layout Design Methodologies for Sub-Wavelength Manufacturing (MLR, JPM, SP), pp. 85–88.
DAC-2001-SchellenbergTCS #design #layout: Adoption of OPC and the Impact on Design and Layout (FMS, OT, LC, BS), pp. 89–92.
DAC-2001-SanieCHM #design #standard: A Practical Application of Full-Feature Alternating Phase-Shifting Technology for a Phase-Aware Standard-Cell Design Flow (MS, MC, PH, VM), pp. 93–96.
DAC-2001-ChangWM #logic #using: Layout-Driven Hot-Carrier Degradation Minimization Using Logic Restructuring Techniques (CWJC, KW, MMS), pp. 97–102.
DAC-2001-MishchenkoSP #algorithm #logic: An Algorithm for Bi-Decomposition of Logic Functions (AM, BS, MAP), pp. 103–108.
DAC-2001-GolumbicMR #recognition #using: Factoring and Recognition of Read-Once Functions using Cographs and Normality (MCG, AM, UR), pp. 109–114.
DAC-2001-Ciriani #logic #using: Logic Minimization using Exclusive OR Gates (VC), pp. 115–120.
DAC-2001-SavojR #communication #design: Design of Half-Rate Clock and Data Recovery Circuits for Optical Communication Systems (JS, BR), pp. 121–126.
DAC-2001-GorenSW #analysis #novel #pipes and filters #probability: A Novel Method for Stochastic Nonlinearity Analysis of a CMOS Pipeline ADC (DG, ES, IAW), pp. 127–132.
DAC-2001-GanesanV #behaviour #clustering #synthesis: Behavioral Partitioning in the Synthesis of Mixed Analog-Digital Systems (SG, RV), pp. 133–138.
DAC-2001-VerhaegenG #analysis #linear #performance #scalability: Efficient DDD-based Symbolic Analysis of Large Linear Analog Circuits (WV, GGEG), pp. 139–144.
DAC-2001-Pomeranz #random #testing: Random Limited-Scan to Improve Random Pattern Testing of Scan Circuits (IP), pp. 145–150.
DAC-2001-BayraktarogluO #reduction: Test Volume and Application Time Reduction Through Scan Chain Concealment (IB, AO), pp. 151–155.
DAC-2001-PomeranzR #approach #testing: An Approach to Test Compaction for Scan Circuits that Enhances At-Speed Testing (IP, SMR), pp. 156–161.
DAC-2001-WangC #generative #performance #testing: Generating Efficient Tests for Continuous Scan (SJW, SNC), pp. 162–165.
DAC-2001-ChandraC #power management #testing: Combining Low-Power Scan Testing and Test Data Compression for System-on-a-Chip (AC, KC), pp. 166–169.
DAC-2001-SchaumontVKS #configuration management: A Quick Safari Through the Reconfiguration Jungle (PS, IV, KK, MS), pp. 172–177.
DAC-2001-SalefskiC #configuration management: Re-Configurable Computing in Wireless (BS, LC), pp. 178–183.
DAC-2001-WangKMR #hardware #set: Hardware/Software Instruction Set Configurability for System-on-Chip Processors (AW, EK, DEM, CR), pp. 184–188.
DAC-2001-AlpertHSV #resource management: A Practical Methodology for Early Buffer and Wire Resource Allocation (CJA, JH, SSS, PV), pp. 189–194.
DAC-2001-BozorgzadehKS #flexibility: Creating and Exploiting Flexibility in Steiner Trees (EB, RK, MS), pp. 195–198.
DAC-2001-LepakLH #constraints: Simultaneous Shield Insertion and Net Ordering under Explicit RLC Noise Constraint (KML, IL, LH), pp. 199–202.
DAC-2001-FanLWC #2d #design #on the: On Optimum Switch Box Designs for 2-D FPGAs (HF, JL, YLW, CCC), pp. 203–208.
DAC-2001-BhanjaR #dependence #modelling #network #probability #process #using: Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks (SB, NR), pp. 209–214.
DAC-2001-KimCL #estimation #logic: A Static Estimation Technique of Power Sensitivity in Logic Circuits (TK, KSC, CLL), pp. 215–219.
DAC-2001-SinhaC #energy #named #profiling #web: JouleTrack — A Web Based Tool for Software Energy Profiling (AS, AC), pp. 220–225.
DAC-2001-VelevB #effectiveness #satisfiability #using #verification: Effective Use of Boolean Satisfiability Procedures in the Formal Verification of Superscalar and VLIW Microprocessors (MNV, REB), pp. 226–231.
DAC-2001-KuehlmannGP #reasoning: Circuit-based Boolean Reasoning (AK, MKG, VP), pp. 232–237.
DAC-2001-SchollB #equivalence #implementation: Checking Equivalence for Partial Implementations (CS, BB), pp. 238–243.
DAC-2001-Bentley #validation: Validating the Intel Pentium 4 Microprocessor (BB), pp. 244–248.
DAC-2001-Albin #verification: Nuts and Bolts of Core and SoC Verification (KA), pp. 249–252.
DAC-2001-OzgunerMDWSH #design #education #logic #verification: Teaching Future Verification Engineers: The Forgotten Side of Logic Design (FÖ, DWM, JD, BW, JS, LH), pp. 253–255.
DAC-2001-GrahmC #integration #reuse: SoC Integration of Reusable Baseband Bluetooth IP (TG, BC), pp. 256–261.
DAC-2001-Zeijl #challenge: One-chip Bluetooth ASIC Challenges (PTMvZ), p. 262.
DAC-2001-TheobaldN #distributed #optimisation #synthesis: Transformations for the Synthesis and Optimization of Asynchronous Distributed Control (MT, SMN), pp. 263–268.
DAC-2001-GuptaSKDGN #design #synthesis: Speculation Techniques for High Level Synthesis of Control Intensive Designs (SG, NS, SK, NDD, RKG, AN), pp. 269–272.
DAC-2001-Bondalapati #architecture #configuration management #using: Parallelizing DSP Nested Loops on Reconfigurable Architectures using Data Context Switching (KB), pp. 273–276.
DAC-2001-PeymandoustM #algebra #algorithm #synthesis #using: Using Symbolic Algebra in Algorithmic Level DSP Synthesis (AP, GDM), pp. 277–282.
DAC-2001-McDonaldB #analysis #simulation #using: Computing Logic-Stage Delays Using Circuit Simulation and Symbolic Elmore Analysis (CBM, REB), pp. 283–288.
DAC-2001-ChenGB: A New Gate Delay Model for Simultaneous Switching and Its Applications (LCC, SKG, MAB), pp. 289–294.
DAC-2001-BaiBH #analysis #power management: Static Timing Analysis Including Power Supply Noise Effect on Propagation Delay in VLSI Circuits (GB, SB, INH), pp. 295–300.
DAC-2001-WuHCWW #algorithm #generative #multi #scheduling: Simulation-Based Test Algorithm Generation and Port Scheduling for Multi-Port Memories (CFW, CTH, KLC, CWW, CWW), pp. 301–306.
DAC-2001-YangPT #bound: Improving Bus Test Via IDDT and Boundary Scan (SYY, CAP, MTA), pp. 307–312.
DAC-2001-RaahemifarA #detection #fault: Fault Characterizations and Design-for-Testability Technique for Detecting IDDQ Faults in CMOS/BiCMOS Circuits (KR, MA), pp. 313–316.
DAC-2001-ChenBD #embedded #fault #testing #using: Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores (LC, XB, SD), pp. 317–320.
DAC-2001-BeattieP #modelling: Inductance 101: Modeling and Extraction (MWB, LTP), pp. 323–328.
DAC-2001-GalaBWZZ #analysis #design: Inductance 101: Analysis and Design Issues (KG, DB, JW, VZ, MZ), pp. 329–334.
DAC-2001-BeattieP01a #modelling: Modeling Magnetic Coupling for On-Chip Interconnect (MWB, LTP), pp. 335–340.
DAC-2001-LuCYP #metric #modelling: Min/max On-Chip Inductance Models and Delay Metrics (YCL, MC, TY, LTP), pp. 341–346.
DAC-2001-Gebotys #embedded #memory management: Utilizing Memory Bandwidth in DSP Embedded Processors (CHG), pp. 347–352.
DAC-2001-UdayanarayananC #code generation: Address Code Generation for Digital Signal Processors (SU, CC), pp. 353–358.
DAC-2001-RamanujamHKN #embedded #memory management #requirements: Reducing Memory Requirements of Nested Loops for Embedded Systems (JR, JH, MTK, AN), pp. 359–364.
DAC-2001-KjeldsbergCA #data-driven #detection #estimation: Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications (PGK, FC, EJA), pp. 365–370.
DAC-2001-ZhaoS #algorithm #pattern matching: A New Structural Pattern Matching Algorithm for Technology Mapping (MZ, SSS), pp. 371–376.
DAC-2001-KarandikarS #logic: Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect (SKK, SSS), pp. 377–382.
DAC-2001-SinghMM #latency: Latency and Latch Count Minimization in Wave Steered Circuits (AS, AM, MMS), pp. 383–388.
DAC-2001-CongR #clustering #multi: Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping (JC, MR), pp. 389–394.
DAC-2001-CarballoD #collaboration #constraints #design #heuristic: Application of Constraint-Based Heuristics in Collaborative Design (JAC, SWD), pp. 395–400.
DAC-2001-BrglezL #design #distributed: A Universal Client for Distributed Networked Design and Computing (FB, HL), pp. 401–406.
DAC-2001-KirovskiDP #design: Hypermedia-Aided Design (DK, MD, MP), pp. 407–412.
DAC-2001-KuhnOWREK #framework #hardware #object-oriented #specification #synthesis #verification: A Framework for Object Oriented Hardware Specification, Verification, and Synthesis (TK, TO, MW, WR, ME, YK), pp. 413–418.
DAC-2001-ChinneryNK: Achieving 550Mhz in an ASIC Methodology (DGC, BN, KK), pp. 420–425.
DAC-2001-NorthropL #design: A Semi-Custom Design Flow in High-Performance Microprocessor Design (GAN, PFL), pp. 426–431.
DAC-2001-RichPS #design #perspective: Reducing the Frequency Gap Between ASIC and Custom Designs: A Custom Perspective (SER, MJP, JS), pp. 432–437.
DAC-2001-ShinKL #analysis #energy #scheduling #using: Low-Energy Intra-Task Voltage Scheduling Using Static Timing Analysis (DS, JK, SL), pp. 438–443.
DAC-2001-LuoJ #distributed #embedded #realtime #scheduling: Battery-Aware Static Scheduling for Distributed Real-Time Embedded Systems (JL, NKJ), pp. 444–449.
DAC-2001-PopEPP #approach #design #distributed #embedded #incremental: An Approach to Incremental Design of Distributed Embedded Systems (PP, PE, TP, ZP), pp. 450–455.
DAC-2001-YuYW #representation #synthesis #using: Signal Representation Guided Synthesis Using Carry-Save Adders For Synchronous Data-path Circuits (ZY, MLY, ANWJ), pp. 456–461.
DAC-2001-MathurS #analysis #precise #using: Improved Merging of Datapath Operators using Information Content and Required Precision Analysis (AM, SS), pp. 462–467.
DAC-2001-ParkK #representation #synthesis: Digital Filter Synthesis Based on Minimal Signed Digit Representation (ICP, HJK), pp. 468–473.
DAC-2001-Qu #component #detection: Publicly Detectable Techniques for the Protection of Virtual Components (GQ), pp. 474–479.
DAC-2001-MajumdarW #combinator #satisfiability #using: Watermarking of SAT using Combinatorial Isolation Lemmas (RM, JLW), pp. 480–485.
DAC-2001-WolfeWP #clustering #graph: Watermarking Graph Partitioning Solutions (GW, JLW, MP), pp. 486–489.
DAC-2001-KoushanfarQ #hardware: Hardware Metering (FK, GQ), pp. 490–493.
DAC-2001-Restle #design #visualisation: Technical Visualizations in VLSI Design (PR), pp. 494–499.
DAC-2001-SolomonH #layout #using: Using Texture Mapping with Mipmapping to Render a VLSI Layout (JS, MH), pp. 500–505.
DAC-2001-Najork #algorithm #animation: Web-based Algorithm Animation (MN), pp. 506–511.
DAC-2001-PetrovO #architecture #embedded: Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors (PP, AO), pp. 512–517.
DAC-2001-LyonnardYBJ #architecture #automation #generative #multi: Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip (DL, SY, AB, AAJ), pp. 518–523.
DAC-2001-SimunicBAGM #power management #scalability: Dynamic Voltage Scaling and Power Management for Portable Systems (TS, LB, AA, PWG, GDM), pp. 524–529.
DAC-2001-MoskewiczMZZM #named #performance #satisfiability: Chaff: Engineering an Efficient SAT Solver (MWM, CFM, YZ, LZ, SM), pp. 530–535.
DAC-2001-GuptaGYA #detection #image #satisfiability: Dynamic Detection and Removal of Inactive Clauses in SAT with Application in Image Computation (AG, AG, ZY, PA), pp. 536–541.
DAC-2001-WhittemoreKS #incremental #named #satisfiability: SATIRE: A New Incremental Satisfiability Engine (JW, JK, KAS), pp. 542–545.
DAC-2001-GizdarskiF #complexity #framework #learning: A Framework for Low Complexity Static Learning (EG, HF), pp. 546–549.
DAC-2001-TanS #modelling #network #optimisation #performance: Fast Power/Ground Network Optimization Based on Equivalent Circuit Modeling (SXDT, CJRS), pp. 550–554.
DAC-2001-UchinoC #energy: An Interconnect Energy Model Considering Coupling Effects (TU, JC), pp. 555–558.
DAC-2001-ChenC #analysis #grid #performance #power management #scalability: Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods (THC, CCPC), pp. 559–562.
DAC-2001-DanielSW #analysis #performance #using: Using Conduction Modes Basis Functions for Efficient Electromagnetic Analysis of On-Chip and Off-Chip Interconnect (LD, ALSV, JW), pp. 563–566.
DAC-2001-AjamiBPG #analysis #performance: Analysis of Non-Uniform Temperature-Dependent Interconnect Performance in High Performance ICs (AHA, KB, MP, LPPPvG), pp. 567–572.
DAC-2001-JaniszewskiHM #design #performance #reuse: VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers (IJ, BH, HM), pp. 573–578.
DAC-2001-KarriWMK #concurrent #detection #fault #symmetry: Concurrent Error Detection of Fault-Based Side-Channel Cryptanalysis of 128-Bit Symmetric Block Ciphers (RK, KW, PM, YK), pp. 579–585.
DAC-2001-MeguerdichianKMPP #design #named #optimisation: MetaCores: Design and Optimization Techniques (SM, FK, AM, DP, MP), pp. 585–590.
DAC-2001-ReyneriCSL #co-evolution #design #hardware #library: A Hardware/Software Co-design Flow and IP Library Based of SimulinkTM (LMR, FC, AS, LL), pp. 593–598.
DAC-2001-NandiM #analysis #design #embedded #performance: System-Level Power/Performance Analysis for Embedded Systems Design (AN, RM), pp. 599–604.
DAC-2001-TanRLJ #energy #megamodelling: High-level Software Energy Macro-modeling (TKT, AR, GL, NKJ), pp. 605–610.
DAC-2001-ChoiYLR #embedded #industrial #model checking: Model Checking of S3C2400X Industrial Embedded SOC Product (HC, BWY, YTL, HR), pp. 611–616.
DAC-2001-DushinaBG #generative #testing: Semi-Formal Test Generation with Genevieve (JD, MB, DG), pp. 617–622.
DAC-2001-KudlugiHSP #architecture #functional #simulation #transaction #verification: A Transaction-Based Unified Simulation/Emulation Architecture for Functional Verification (MK, SH, CS, DP), pp. 623–628.
DAC-2001-DoboliV #constraints #design #synthesis: Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints (AD, RV), pp. 629–634.
DAC-2001-BazarganOS #architecture #compilation #configuration management #design #physics #scheduling: Integrating Scheduling and Physical Design into a Coherent Compilation Cycle for Reconfigurable Computing Architectures (KB, SO, MS), pp. 635–640.
DAC-2001-BruniBB #design #statistics #synthesis: Statistical Design Space Exploration for Application-Specific Unit Synthesis (DB, AB, LB), pp. 641–646.
DAC-2001-KudlugiST #functional #multi #scheduling #verification: Static Scheduling of Multiple Asynchronous Domains For Functional Verification (MK, CS, RT), pp. 647–652.
DAC-2001-XiaoM #analysis #correlation #functional #identification: Functional Correlation Analysis in Crosstalk Induced Critical Paths Identification (TX, MMS), pp. 653–656.
DAC-2001-YalcinPMBSH #dependence #using: An Advanced Timing Characterization Method Using Mode Dependency (HY, RP, MM, CB, KAS, JPH), pp. 657–660.
DAC-2001-LiouCKK #analysis #performance #probability #statistics: Fast Statistical Timing Analysis By Probabilistic Event Propagation (JJL, KTC, SK, AK), pp. 661–666.
DAC-2001-SgroiSMKMRS #design: Addressing the System-on-a-Chip Interconnect Woes Through Communication-Based Design (MS, MS, AM, KK, SM, JMR, ALSV), pp. 667–672.
DAC-2001-Wingard #integration: MicroNetwork-Based Integration for SOCs (DW), pp. 673–677.
DAC-2001-KarimNDR #architecture #communication #network: On-Chip Communication Architecture for OC-768 Network Processors (FK, AN, SD, RRR), pp. 678–683.
DAC-2001-DallyT #network: Route Packets, Not Wires: On-Chip Interconnection Networks (WJD, BT), pp. 684–689.
DAC-2001-KandemirRIVKP #memory management: Dynamic Management of Scratch-Pad Memory Space (MTK, JR, MJI, NV, IK, AP), pp. 690–695.
DAC-2001-JacomeVP #architecture #clustering: Clustered VLIW Architectures with Predicated Switching (MFJ, GdV, SP), pp. 696–701.
DAC-2001-LapinskiiJV #clustering: High-Quality Operation Binding for Clustered VLIW Datapaths (VSL, MFJ, GdV), pp. 702–707.
DAC-2001-KedingCLM #performance #simulation: Fast Bit-True Simulation (HK, MC, OL, HM), pp. 708–713.
DAC-2001-ZhouSN #analysis #fixpoint: Timing Analysis with Crosstalk as Fixpoints on Complete Lattice (HZ, NVS, WN), pp. 714–719.
DAC-2001-SirichotiyakulBOLZZ #modelling #worst-case: Driver Modeling and Alignment for Worst-Case Delay Noise (SS, DB, CO, RL, VZ, JZ), pp. 720–725.
DAC-2001-ArunachalamBP #analysis #interactive: False Coupling Interactions in Static Timing Analysis (RA, RDB, LTP), pp. 726–731.
DAC-2001-KimJSLK #optimisation #using: Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique (KWK, SOJ, PS, CLL, SMK), pp. 732–737.
DAC-2001-WangRLJ #adaptation #design #energy #optimisation #performance: Input Space Adaptive Design: A High-level Methodology for Energy and Performance Optimization (WW, AR, GL, NKJ), pp. 738–743.
DAC-2001-HenkelL #adaptation #design #named #power management: A2BC: Adaptive Address Bus Coding for Low Power Deep Sub-Micron Designs (JH, HL), pp. 744–749.
DAC-2001-ShinS #design #power management: Coupling-Driven Bus Design for Low-Power Application-Specific Systems (YS, TS), pp. 750–753.
DAC-2001-TaylorDZ #energy #modelling: Modeling and Minimization of Interconnect Energy Dissipation in Nanometer Technologies (CNT, SD, YZ), pp. 754–757.
DAC-2001-KimZP #multi: A True Single-Phase 8-bit Adiabatic Multiplier (SK, CHZ, MCP), pp. 758–763.
DAC-2001-LinC #graph #named #representation #transitive: TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans (JML, YWC), pp. 764–769.
DAC-2001-MaHDCCG #constraints: Floorplanning with Abutment Constraints and L-Shaped/T-Shaped Blocks based on Corner Block List (YM, XH, SD, YC, CKC, JG), pp. 770–775.
DAC-2001-YildizM #clustering #sequence: Improved Cut Sequences for Partitioning Based Placement (MCY, PHM), pp. 776–779.
DAC-2001-HalpinCS #constraints #physics #using: Timing Driven Placement using Physical Net Constraints (BH, CYRC, NS), pp. 780–783.
DAC-2001-BeniniMMMP #architecture #embedded #layout #memory management #synthesis: From Architecture to Layout: Partitioned Memory Synthesis for Embedded Systems-on-Chip (LB, LM, AM, EM, MP), pp. 784–789.
DAC-2001-NouraniA #self: Built-In Self-Test for Signal Integrity (MN, AA), pp. 792–797.
DAC-2001-BanerjeeM #analysis #distributed #novel #optimisation #performance #using: Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects (KB, AM), pp. 798–803.
DAC-2001-MassoudKMW #analysis #difference #induction #modelling: Modeling and Analysis of Differential Signaling for Minimizing Inductive Cross-Talk (YM, JK, DM, JW), pp. 804–809.
DAC-2001-KroeningP #automation #design #pipes and filters: Automated Pipeline Design (DK, WJP), pp. 810–815.
DAC-2001-KohnoM #behaviour #pipes and filters #verification: A New Verification Methodology for Complex Pipeline Behavior (KK, NM), pp. 816–821.
DAC-2001-LeeT #fault #verification: Pre-silicon Verification of the Alpha 21364 Microprocessor Error Handling System (RL, BT), pp. 822–827.
DAC-2001-QuanH #energy #performance #realtime #scheduling: Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors (GQ, XH), pp. 828–833.
DAC-2001-QiuWP #mobile #multi #power management: Dynamic Power Management in a Mobile Multimedia System with Guaranteed Quality-of-Service (QQ, QW, MP), pp. 834–839.
DAC-2001-LiuCBK #constraints #embedded #power management #scheduling: Power-Aware Scheduling under Timing Constraints for Mission-Critical Embedded Systems (JL, PHC, NB, FJK), pp. 840–845.
DAC-2001-ZhangRKJ #3d #architecture #integration: Exploring SOI Device Structures and Interconnect Architectures for 3-Dimensional Integration (RZ, KR, CKK, DBJ), pp. 846–851.
DAC-2001-LeeNCKD #2d #detection: Two-Dimensional Position Detection System with MEMS Accelerometer for MOUSE Applications (SL, GJN, JC, HK, AJD), pp. 852–857.
DAC-2001-SchenkelPZSGA #analysis #optimisation: Mismatch Analysis and Direct Yield Optimization by Spec-Wise Linearization and Feasibility-Guided Search (FS, MP, SZ, RS, HEG, KA), pp. 858–863.

Proceedings of the 38th Design Automation ConferenceDAC, 2001.

Contents (153 items)

Proceedings of the 38th Design Automation Conference
DAC, 2001.