Travelled to:2 × USA
Collaborated with:S.K.Lim M.Pathak J.Yang Y.Lee D.Z.Pan
Talks about:die (2) placement (1) thermal (1) exploit (1) analysi (1) stress (1) layout (1) applic (1) optim (1) coupl (1)
Person: Krit Athikulwongse
DBLP: Athikulwongse:Krit
Contributed to:
20122010Wrote 2 papers:
- DAC-2012-AthikulwongsePL #3d
- Exploiting die-to-die thermal coupling in 3D IC placement (KA, MP, SKL), pp. 741–746.
- DAC-2010-YangALLP #3d #analysis #layout #optimisation
- TSV stress aware timing analysis with applications to 3D-IC layout optimization (JSY, KA, YJL, SKL, DZP), pp. 803–806.