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Travelled to:
2 × USA
Collaborated with:
Y.Ban K.Athikulwongse Y.Lee S.K.Lim D.Z.Pan
Talks about:
layout (2) optim (2) awar (2) analysi (1) stress (1) leakag (1) applic (1) rough (1) model (1) minim (1)

Person: Jae-Seok Yang

DBLP DBLP: Yang:Jae=Seok

Contributed to:

DAC 20112011
DAC 20102010

Wrote 2 papers:

DAC-2011-BanY #layout #modelling #optimisation
Layout aware line-edge roughness modeling and poly optimization for leakage minimization (YB, JSY), pp. 447–452.
DAC-2010-YangALLP #3d #analysis #layout #optimisation
TSV stress aware timing analysis with applications to 3D-IC layout optimization (JSY, KA, YJL, SKL, DZP), pp. 803–806.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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