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Travelled to:
2 × Germany
3 × France
8 × USA
Collaborated with:
Y.Lee Y.Peng J.R.Minz M.Jung D.Z.Pan S.Panth K.Samadi Y.Du M.Pathak M.B.Healy T.Song K.Athikulwongse Y.Tao E.Wong C.Liu M.Ekpanyapong H.S.Lee D.Petranovic D.B.Limbrick X.Zhao M.Scheuermann S.Thyagaraja J.Cong C.Wu J.Mitra Y.Wan J.Yang T.Watewai S.K.Samal M.Saedi J.Cho J.Kim J.Kim B.W.Ku Y.Park K.Park S.Jang J.Choi Y.J.Kim G.Huang M.S.Bakir Y.K.Joshi A.G.Fedorov M.Vittes C.S.Ballapuram G.H.Loh
Talks about:
power (10) tsv (9) optim (7) thermal (5) analysi (5) chip (5) perform (4) packag (4) coupl (4) full (4)

Person: Sung Kyu Lim

DBLP DBLP: Lim:Sung_Kyu

Contributed to:

DAC 20152015
DAC 20142014
DATE 20142014
DAC 20132013
DAC 20122012
DAC 20112011
DATE 20112011
DAC 20102010
DATE 20092009
DATE 20062006
DAC 20042004
DATE v2 20042004
DAC 20002000

Wrote 24 papers:

DAC-2015-PanthSDL #3d #clustering #mobile #power management #trade-off
Tier-partitioning for power delivery vs cooling tradeoff in 3D VLSI for mobile applications (SP, KS, YD, SKL), p. 6.
DAC-2015-PengKPPJCL #3d #architecture #design #policy
Design, packaging, and architectural policy co-optimization for DC power integrity in 3D DRAM (YP, BWK, YSP, KIP, SJJ, JSC, SKL), p. 6.
DAC-2014-JungSWPL #3d #on the #perspective
On Enhancing Power Benefits in 3D ICs: Block Folding and Bonding Styles Perspective (MJ, TS, YW, YP, SKL), p. 6.
DAC-2014-PanthSDL #3d #performance
Power-Performance Study of Block-Level Monolithic 3D-ICs Considering Inter-Tier Performance Variations (SP, KS, YD, SKL), p. 6.
DAC-2014-PengPL #optimisation #performance
Fast and Accurate Full-chip Extraction and Optimization of TSV-to-Wire Coupling (YP, DP, SKL), p. 6.
DAC-2014-SamalPSSDL #3d #modelling #optimisation #performance
Fast and Accurate Thermal Modeling and Optimization for Monolithic 3D ICs (SKS, SP, KS, MS, YD, SKL), p. 6.
DATE-2014-LeeL #3d #gpu #on the #reduction
On GPU bus power reduction with 3D IC technologies (YJL, SKL), pp. 1–6.
DAC-2013-LeeLL #3d
Power benefit study for ultra-high density transistor-level monolithic 3D ICs (YJL, DBL, SKL), p. 10.
DAC-2013-SongLPL #3d #multi #optimisation
Full-chip multiple TSV-to-TSV coupling extraction and optimization in 3D ICs (TS, CL, YP, SKL), p. 7.
DAC-2012-AthikulwongsePL #3d
Exploiting die-to-die thermal coupling in 3D IC placement (KA, MP, SKL), pp. 741–746.
DAC-2012-JungPL #3d #reliability
Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs (MJ, DZP, SKL), pp. 317–326.
DAC-2012-ZhaoSL #3d #analysis
Analysis of DC current crowding in through-silicon-vias and its impact on power integrity in 3D ICs (XZ, MS, SKL), pp. 157–162.
DAC-2011-JungMPL #3d #analysis #optimisation #reliability
TSV stress-aware full-chip mechanical reliability analysis and optimization for 3D IC (MJ, JM, DZP, SKL), pp. 188–193.
DAC-2011-LiuSCKKL #3d #analysis #optimisation
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC (CL, TS, JC, JK, JK, SKL), pp. 783–788.
DATE-2011-HealyL #3d #network #novel
A novel TSV topology for many-tier 3D power-delivery networks (MBH, SKL), pp. 261–264.
DAC-2010-YangALLP #3d #analysis #layout #optimisation
TSV stress aware timing analysis with applications to 3D-IC layout optimization (JSY, KA, YJL, SKL, DZP), pp. 803–806.
DATE-2009-LeeKHBJFL #3d #co-evolution #design #network
Co-design of signal, power, and thermal distribution networks for 3D ICs (YJL, YJK, GH, MSB, YKJ, AGF, SKL), pp. 610–615.
DATE-2009-TaoL #grid #power management
Decoupling capacitor planning with analytical delay model on RLC power grid (YT, SKL), pp. 839–844.
DATE-2006-HealyVEBLLL #architecture #performance #trade-off
Microarchitectural floorplanning under performance and thermal tradeoff (MBH, MV, ME, CSB, SKL, HHSL, GHL), pp. 1288–1293.
DATE-2006-MinzTL #3d
Optical routing for 3D system-on-package (JRM, ST, SKL), pp. 337–338.
DATE-2006-WongL #3d
3D floorplanning with thermal vias (EW, SKL), pp. 878–883.
DAC-2004-EkpanyapongMWLL #architecture #design
Profile-guided microarchitectural floorplanning for deep submicron processor design (ME, JRM, TW, HHSL, SKL), pp. 634–639.
DATE-v2-2004-MinzPL #3d
Net and Pin Distribution for 3D Package Global Routing (JRM, MP, SKL), pp. 1410–1411.
DAC-2000-CongLW #clustering #multi #performance
Performance driven multi-level and multiway partitioning with retiming (JC, SKL, CW), pp. 274–279.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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