Travelled to:1 × France
1 × Germany
Collaborated with:G.Masera M.Zamboni C.Condo M.Martina S.Tota M.R.Casu L.Rostagno F.Viglione G.Piccinini
Talks about:base (2) multiprocessor (1) architectur (1) logarithm (1) rediscov (1) topolog (1) network (1) messag (1) memori (1) latenc (1)
Person: Massimo Ruo Roch
DBLP: Roch:Massimo_Ruo
Contributed to:
2014
20102000Wrote 3 papers:
- PDP-2014-CondoMRM #latency
- Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications (CC, MM, MRR, GM), pp. 418–423.
- DATE-2010-TotaCRRZ #architecture #hybrid #message passing #multi #named
- MEDEA: a hybrid shared-memory/message-passing multiprocessor NoC-based architecture (ST, MRC, MRR, LR, MZ), pp. 45–50.
- DATE-2000-ViglioneMPRZ
- A 50 Mbit/s Iterative Turbo-Decoder (FV, GM, GP, MRR, MZ), pp. 176–180.