Travelled to:2 × France
4 × Germany
Collaborated with:M.Martina C.Condo S.Zezza M.R.Roch F.Quaglio F.Vacca P.Bernardi M.S.Reorda C.Castellano A.Tarable F.Viglione G.Piccinini M.Zamboni A.Molino L.Sterpone M.Violante M.S.Amirhossein P.M.Ros A.Bonanno M.Crepaldi D.Demarchi
Talks about:decod (4) base (3) approach (2) network (2) turbo (2) ldpc (2) chip (2) low (2) interconnect (1) architectur (1)
Person: Guido Masera
DBLP: Masera:Guido
Contributed to:
2015
201420122008200620042000Wrote 8 papers:
- DATE-2015-AmirhosseinRBCM #power management
- An all-digital spike-based ultra-low-power IR-UWB dynamic average threshold crossing scheme for muscle force wireless transmission (MSA, PMR, AB, MC, MM, DD, GM), pp. 1479–1484.
- PDP-2014-CondoMRM #latency
- Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications (CC, MM, MRR, GM), pp. 418–423.
- DATE-2012-CondoMM #architecture
- A Network-on-Chip-based turbo/LDPC decoder architecture (CC, MM, GM), pp. 1525–1530.
- DATE-2008-ZezzaM #implementation
- VLSI implementation of SISO arithmetic decoders for joint source channel coding (SZ, GM), pp. 1075–1078.
- DATE-DF-2006-MartinaMMVSV #approach #programmable
- A new approach to compress the configuration information of programmable devices (MM, GM, AM, FV, LS, MV), pp. 48–51.
- DATE-DF-2006-QuaglioVCTM #flexibility #framework
- Interconnection framework for high-throughput, flexible LDPC decoders (FQ, FV, CC, AT, GM), pp. 124–129.
- DATE-2005-BernardiMQR04 #approach #logic #testing #using
- Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study (PB, GM, FQ, MSR), pp. 228–233.
- DATE-2000-ViglioneMPRZ
- A 50 Mbit/s Iterative Turbo-Decoder (FV, GM, GP, MRR, MZ), pp. 176–180.