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Travelled to:
1 × Cyprus
1 × France
1 × Germany
Collaborated with:
F.Catthoor P.Raghavan A.Lambrechts D.Verkest H.Corporaal T.V.Aa F.Barat G.Deconinck
Talks about:
processor (2) thread (2) regist (2) architectur (1) distribut (1) asymmetr (1) schedul (1) control (1) explor (1) energi (1)

Person: Murali Jayapala

DBLP DBLP: Jayapala:Murali

Contributed to:

DATE 20072007
DATE 20062006
SAC 20042004

Wrote 3 papers:

DATE-2007-RaghavanLJCVC #embedded #power management #symmetry
Very wide register: an asymmetric register file organization for low power embedded processors (PR, AL, MJ, FC, DV, HC), pp. 1066–1071.
DATE-2006-RaghavanLJCV #architecture #distributed #multi #thread
Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors (PR, AL, MJ, FC, DV), pp. 339–344.
SAC-2004-JayapalaABDCC #energy #optimisation #scheduling
L0 buffer energy optimization through scheduling and exploration (MJ, TVA, FB, GD, FC, HC), pp. 905–906.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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