BibSLEIGH — Diederik

Travelled to:

5 × Germany
6 × France
6 × USA

Collaborated with:

F.Catthoor H.D.Man S.Vernalde R.Lauwereins V.Nollet J.Mignolet S.Vercauteren P.Raghavan B.Mei A.Lambrechts M.Jayapala G.G.d.Jong S.Guccione I.Bolsens D.Desmet J.Kunkel F.Schirrmeister J.v.d.Steen M.Miranda C.Ykman-Couvreur P.Avasare F.Vermeulen B.Lin T.Marescaux A.Vandecappelle E.Brockmeyer J.Ryckaert R.Baert K.Croes H.Corporaal P.Coene J.Lambrecht A.Nikologiannis G.E.Konstantoulakis I.Karageorgos M.Stucchi Z.Tokei S.Sakhare W.Dehaene C.Wong P.Marchal P.Yang A.S.Prayati N.Cossement J.L.d.S.Jr. S.Wuytack P.Six A.Mallik P.Zuber T.Liu B.Chava B.Ballal P.R.D.Bario M.Badaroglu A.Mercha

Talks about:

system (9) design (5) reconfigur (4) level (4) data (4) use (4) architectur (3) methodolog (3) processor (3) softwar (3)

Person: Diederik Verkest

DBLP: Verkest:Diederik

Contributed to:

2015

2013

2007

2006

2005

2004

2003

2002

2001

2000

1999

1998

Wrote 19 papers:

DATE-2015-KarageorgosSRRT #multi #variability: Impact of interconnect multiple-patterning variability on SRAMs (IK, MS, PR, JR, ZT, DV, RB, SS, WD), pp. 609–612.
DAC-2013-MallikZLCBBBCRBMV #analysis #evaluation #framework #named: TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes (AM, PZ, TTL, BC, BB, PRDB, RB, KC, JR, MB, AM, DV), p. 6.
DATE-2007-RaghavanLJCVC #embedded #power management #symmetry: Very wide register: an asymmetric register file organization for low power embedded processors (PR, AL, MJ, FC, DV, HC), pp. 1066–1071.
DATE-2006-RaghavanLJCV #architecture #distributed #multi #thread: Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors (PR, AL, MJ, FC, DV), pp. 339–344.
DATE-2005-NolletAMV #low cost #migration: Low Cost Task Migration Initiation in a Heterogeneous MP-SoC (VN, PA, JYM, DV), pp. 252–253.
DAC-2004-NolletMVMV #network: Operating-system controlled network on chip (VN, TM, DV, JYM, SV), pp. 256–259.
DATE-v2-2004-MeiVVL #architecture #case study #configuration management #design #matrix: Design Methodology for a Tightly Coupled VLIW/Reconfigurable Matrix Architecture: A Case Study (BM, SV, DV, RL), pp. 1224–1229.
DATE-2003-MeiVVML #architecture #configuration management #parallel #scheduling #using: Exploiting Loop-Level Parallelism on Coarse-Grained Reconfigurable Architectures Using Modulo Scheduling (BM, SV, DV, HDM, RL), pp. 10296–10301.
DATE-2003-MignoletNCVVL #configuration management #design #framework: Infrastructure for Design and Management of Relocatable Tasks in a Heterogeneous Reconfigurable System-on-Chip (JYM, VN, PC, DV, SV, RL), pp. 10986–10993.
DAC-2002-Ykman-CouvreurLVCNK #memory management #network #optimisation #performance: System-level performance optimization of the data queueing memory management in high-speed network processors (CYC, JL, DV, FC, AN, GEK), pp. 518–523.
DATE-2002-GuccioneVB #configuration management #design #platform: Design Technology for Networked Reconfigurable FPGA Platforms (SG, DV, IB), pp. 994–997.
DATE-2001-WongMYCMPCLV #concurrent #summary: Task concurrency management methodology summary (CW, PM, PY, FC, HDM, ASP, NC, RL, DV), p. 813.
DAC-2000-DesmetVM #generative #operating system: Operating system based software generation for systems-on-chip (DD, DV, HDM), pp. 396–401.
DATE-2000-VerkestKS #c++ #design #using: System Level Design Using C++ (DV, JK, FS), pp. 74–81.
DATE-2000-VermeulenCMV #embedded #reuse: Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications (FV, FC, HDM, DV), pp. 92–98.
DAC-1999-VandecappelleMBCV #design #feedback #memory management #multi #using: Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback (AV, MM, EB, FC, DV), pp. 327–332.
DATE-1999-VercauterenSV #constraints #generative #hardware #interface #realtime #synthesis: Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time Constraints (SV, JvdS, DV), pp. 556–561.
DAC-1998-SilvaYMCWJCVSM #data transfer #performance #synthesis: Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer (JLdSJ, CYC, MM, KC, SW, GGdJ, FC, DV, PS, HDM), pp. 76–81.
DATE-1998-VercauterenVJL #analysis #partial order #performance #using #verification: Efficient Verification using Generalized Partial Order Analysis (SV, DV, GGdJ, BL), pp. 782–789.