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Travelled to:
1 × France
Collaborated with:
R.Vadlamani W.Burleson R.Tessier
Talks about:
interconnect (1) subsystem (1) processor (1) multicor (1) support (1) monitor (1)

Person: Sailaja Madduri

DBLP DBLP: Madduri:Sailaja

Contributed to:

DATE 20092009

Wrote 1 papers:

DATE-2009-MadduriVBT #manycore #monitoring
A monitor interconnect and support subsystem for multicore processors (SM, RV, WB, RT), pp. 761–766.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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