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Travelled to:
1 × France
1 × Germany
Collaborated with:
R.Tessier J.Zhao W.P.Burleson S.Madduri W.Burleson
Talks about:
multicor (2) interconnect (1) subsystem (1) processor (1) support (1) monitor (1) modular (1) stabil (1) redund (1) error (1)

Person: Ramakrishna Vadlamani

DBLP DBLP: Vadlamani:Ramakrishna

Contributed to:

DATE 20102010
DATE 20092009

Wrote 2 papers:

DATE-2010-VadlamaniZBT #adaptation #composition #fault #manycore #using
Multicore soft error rate stabilization using adaptive dual modular redundancy (RV, JZ, WPB, RT), pp. 27–32.
DATE-2009-MadduriVBT #manycore #monitoring
A monitor interconnect and support subsystem for multicore processors (SM, RV, WB, RT), pp. 761–766.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.