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Travelled to:
1 × Germany
3 × France
5 × USA
Collaborated with:
T.Wolf J.Zhao W.Burleson R.Vadlamani W.Xu I.G.Harris D.Gomez-Prado M.J.Ciesielski M.Kudlugi C.Selvidge K.Hu T.Teixeira H.Chandrikakutty D.Unnikrishnan S.(.Lu W.P.Burleson S.Madduri M.Kainth L.Krishnan C.Narayana S.G.Virupaksha
Talks about:
processor (4) monitor (3) hardwar (3) system (3) fpga (3) interconnect (2) multicor (2) network (2) level (2) soft (2)

Person: Russell Tessier

DBLP DBLP: Tessier:Russell

Contributed to:

DATE 20152015
DAC 20142014
DAC 20132013
DATE 20132013
DATE 20102010
DATE 20092009
LCTES 20072007
DAC 20012001
DAC 20002000

Wrote 10 papers:

DATE-2015-KainthKNVT #obfuscation
Hardware-assisted code obfuscation for FPGA soft microprocessors (MK, LK, CN, SGV, RT), pp. 127–132.
DAC-2014-HuWTT #hardware #monitoring #network #security
System-Level Security for Network Processors with Hardware Monitors (KH, TW, TT, RT), p. 6.
DAC-2013-ChandrikakuttyUTW #hardware #monitoring #network
High-performance hardware monitors to protect network processors from data plane attacks (HC, DU, RT, TW), p. 6.
DATE-2013-Gomez-PradoCT #latency #optimisation #using
FPGA latency optimization using system-level transformations and DFG restructuring (DGP, MJC, RT), pp. 1553–1558.
DATE-2013-ZhaoLBT #detection #manycore #probability #runtime
Run-time probabilistic detection of miscalibrated thermal sensors in many-core systems (JZ, S(L, WB, RT), pp. 1395–1398.
DATE-2010-VadlamaniZBT #adaptation #composition #fault #manycore #using
Multicore soft error rate stabilization using adaptive dual modular redundancy (RV, JZ, WPB, RT), pp. 27–32.
DATE-2009-MadduriVBT #manycore #monitoring
A monitor interconnect and support subsystem for multicore processors (SM, RV, WB, RT), pp. 761–766.
LCTES-2007-XuT #named
Tetris: a new register pressure control technique for VLIW processors (WX, RT), pp. 113–122.
DAC-2001-KudlugiST #functional #multi #scheduling #verification
Static Scheduling of Multiple Asynchronous Domains For Functional Verification (MK, CS, RT), pp. 647–652.
DAC-2000-HarrisT #architecture #clustering #testing
Interconnect testing in cluster-based FPGA architectures (IGH, RT), pp. 49–54.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.