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Travelled to:
1 × Germany
1 × USA
Collaborated with:
D.Z.Pan A.Chakraborty P.Yu A.Ramalingam D.Wang
Talks about:
variat (2) model (2) time (2) lithographi (1) statist (1) silicon (1) process (1) leverag (1) analysi (1) strain (1)

Person: Sean X. Shi

DBLP DBLP: Shi:Sean_X=

Contributed to:

DATE 20082008
DAC 20062006

Wrote 3 papers:

DATE-2008-ChakrabortySP #layout #optimisation
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices (AC, SXS, DZP), pp. 849–855.
DATE-2008-ShiRWP #analysis #modelling #statistics
Latch Modeling for Statistical Timing Analysis (SXS, AR, DW, DZP), pp. 1136–1141.
DAC-2006-YuSP #modelling #process
Process variation aware OPC with variational lithography modeling (PY, SXS, DZP), pp. 785–790.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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